An Artificial Neural Networks based Temperature Prediction Framework for Network-on-Chip based Multicore Platform

Continuous improvement in silicon process technologies has made possible the integration of hundreds of cores on a single chip. However, power and heat have become dominant constraints in designing these massive multicore chips causing issues with reliability, timing variations and reduced lifetime of the chips. Dynamic Thermal Management (DTM) is a solution to avoid high temperatures on the die. Typical DTM schemes only address core level thermal issues. However, the Network-on-chip (NoC) paradigm, which has emerged as an enabling methodology for integrating hundreds to thousands of cores on the same die can contribute significantly to the thermal issues. Moreover, the typical DTM is triggered reactively based on temperature measurements from on-chip thermal sensor requiring long reaction times whereas predictive DTM method estimates future temperature in advance, eliminating the chance of temperature overshoot. Artificial Neural Networks (ANNs) have been used in various domains for modeling and prediction with high accuracy due to its ability to learn and adapt. This thesis concentrates on designing an ANN prediction engine to predict the thermal profile of the cores and Network-on-Chip elements of the chip. This thermal profile of the chip is then used by the predictive DTM that combines both core level and network level DTM techniques. On-chip wireless interconnect which is recently envisioned to enable energy-efficient data exchange between cores in a multicore environment, will be used to provide a broadcast-capable medium to efficiently distribute thermal control messages to trigger and manage the DTM schemes

Combined Dynamic Thermal Management Exploiting Broadcast-Capable Wireless Network-on-Chip Architecture

With the continuous scaling of device dimensions, the number of cores on a single die is constantly increasing. This integration of hundreds of cores on a single die leads to high power dissipation and thermal issues in modern Integrated Circuits (ICs). This causes problems related to reliability, timing violations and lifetime of electronic devices. Dynamic Thermal Management (DTM) techniques have emerged as potential solutions that mitigate the increasing temperatures on a die. However, considering the scaling of system sizes and the adoption of the Network-on-Chip (NoC) paradigm to serve as the interconnection fabric exacerbates the problem as both cores and NoC elements contribute to the increased heat dissipation on the chip. Typically, DTM techniques can either be proactive or reactive. Proactive DTM techniques, where the system has the ability to predict the thermal profile of the chip ahead of time are more desirable than reactive DTM techniques where the system utilizes thermal sensors to determine the current temperature of the chip. Moreover, DTM techniques either address core or NoC level thermal issues separately. Hence, this thesis proposes a combined proactive DTM technique that integrates both core level and NoC level DTM techniques. The combined DTM mechanism includes a dynamic temperature-aware routing approach for the NoC level elements, and includes task reallocation heuristics for the core level elements. On-chip wireless interconnects recently envisioned to enable energy-efficient data exchange between cores in a multicore chip will be used to provide a broadcast-capable medium to efficiently distribute thermal control messages to trigger and manage the DTM. Combining the proactive DTM technique with on-chip wireless interconnects, the on-chip temperature is restricted within target temperatures without significantly affecting the performance of the NoC based interconnection fabric of the multicore chip

On the Analysis of the Internet from a Geographic and Economic Perspective via BGP Raw Data

The Internet is nowadays an integral part of the everyone's life, and will become even more important for future generations. Proof of that is the exponential growth of the number of people who are introduced to the network through mobile phones and smartphones and are connected 24/7. Most of them rely on the Internet even for common services, such as online personal bank accounts, or even having a videoconference with a colleague living across the ocean. However, there are only a few people who are aware of what happens to their data once sent from their own devices towards the Internet, and an even smaller number -- represented by an elite of researchers -- have an overview of the infrastructure of the real Internet. Researchers have attempted during the last years to discover details about the characteristics of the Internet in order to create a model on which it would be possible to identify and address possible weaknesses of the real network. Despite several efforts in this direction, currently no model is known to represent the Internet effectively, especially due to the lack of data and the excessive coarse granularity applied by the studies done to date. This thesis addresses both issues considering Internet as a graph whose nodes are represented by Autonomous Systems (AS) and connections are represented by logical connections between ASes. In the first instance, this thesis has the objective to provide new algorithms and heuristics for studying the Internet at a level of granularity considerably more relevant to reality, by introducing economic and geographical elements that actually limit the number of possible paths between the various ASes that data can undertake. Based on these heuristics, this thesis also provides an innovative methodology suitable to quantify the completeness of the available data to identify which ASes should be involved in the BGP data collection process as feeders in order to get a complete and real view of the core of the Internet. Although the results of this methodology highlights that current BGP route collectors are not able to obtain data regarding the vast majority of the ASes part of the core of the Internet, the situation can still be improved by creating new services and incentives to attract the ASes identified by the previous methodology and introduce them as feeders of a BGP route collector

L.: An analysis of convergence delay in path vector routing protocols

Path vector routing protocols such as BGP are known to suffer from slow convergence. In response a number of convergence enhancements have been proposed, but convergence dynamics have yet to be well understood and there has been no general framework to assess and compare the various improvement algorithms. In this paper we present a general framework to analyze the convergence delay bounds of path vector routing protocols, under the assumption of shortest path policy and single link failure. Our framework takes into account important factors including network connectivity, failure location, and message processing delay. It applies to all path vector protocol variants(standard path vector protocol and convergence improvement algorithms) and allows us to develop analytical bounds that were not previously available, such as the delay bounds for path fail-over for BGP and most of the convergence enhancements. Our analysis shows that BGP fail-over delay bounds are determined largely by a combination of two factors: 1) the distance between the failure and the prefix origin and, 2) the length of the longest alternate path used to reach the destination after the failure. These factors are captured formally and can explain why existing convergence enhancements often provide only limited improvements in fail-over events. Furthermore, explicitly modeling message processing delay reveals insights into the impacts of topology structure (e.g. richness in connectivity) and different effectiveness of different enhancements. These new results allow one to better understand the behavior of various path vector protocols under given topology structure, network size, and message delays