An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

Clock generator cores play an increasingly important role in the VU1 design of embedded microprocessors supporting specialized power management modes. We present a fully digital. standardcell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation. the circuit features a 16 ps jitter, 19.5-to-79 MHz frequency range with a39KHz input. and less than 50 clock cycles wakeup time. © 2001 IEEE