An Algorithm for VLSI Implementation of Highly Efficient Cubic-Polynomial Evaluation

Abstract ⎯ In this paper, we present a novel cubic-polynomial evaluation algorithm. It is suitable for VLSI implementation and the computational cost is reduced to about 66 % of the previously reported method. I. CBIC-POLYNOMIAL EVALUATION ALGORITHM Cubic-polynomial evaluation is a commonly used method in measurement and instrumentation [1], [2]. Among the applications involving cubic-polynomial evaluation, there exist a lot of cases that the measurement is an iterative process, dual-integration analog-to-digital conversion for example. Direct evaluation after the measurement is of low efficiency, since the processing module is idle during the measurement. High computational efficiency can be achieved through iterative method. An iterative cubic-polynomial algorithm was proposed by P.Mathias and L.Patnaik [3]. Their algorithm is based on the idea of systolic array and requires 3 operations at each step. In this paper, we propose an algorithm that employs only 2 operations at each step. So higher computational efficiency is achieved. A general form of cubic-polynomial is: