An Adaptive Viterbi Decoder on the Dynamically Reconfigurable Processor

Abstract — In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics ’ DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3 % and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long. I