An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers

A processor for the adaptation of the coeflcients in high throughput adaptive equaliz-ers will be presented. The accumulation operation- fundumental basis G $the adaptation process- is split into two steps: A$ne-grain carry-save accumulation-with timesharing factor 2 collects the products of estimated error and inpu! symbols over a blocklength of 16 input symbols and operates at twice the symbol rate; a master accumulator with time-sharing factor 32 collects the block-sums from 16jne-grain accumulators, multiplies them with the adaptation constant and carries out theJinal vector merging opertztion, saturation, tap leakage and radix-4 Booth recoding. Three steps to reduce the power consumption of the $ne-grain accumulators will be presented and evaluated for a 14-bit-wide accumula-tor: The suppression oj one state oj the redundant codes jor the value "1 " in the carry save digit alphabet, i.e. (0, l} or { l,O}, reduces the power consumption by 5.5%; The redundancy-reduced digit alphabet can be exploited to reduce the transistor count of the jbllowing full adder by one third, resulting in U signiJicunt input cupucity reduction which increases the maxiniuin clockfrsquency by nearly 15 % and achieves a further reduction of power consumption of 2.7%; Finally an optimized sign extension logic reduces the capaci-tive load of the input sign bits by 70%, eliminates six of the,full adders in the sign extension slices and increases the power reduction to 19.2%. The maximum clock frequency of the accumulator could be increased by 18 % due to the reduced internal load>;.