An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs

Aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (Additive White Gaussian Noise). It shall be shown that the detector allows the carrier synchronization PLL (Phase Locked Loop) to achieve optimal performance during both the acquisition and tracking operation modes. The conditions necessary for this optimality to be achieved will be discussed, and it shall be shown that they are quite reasonable and allow the proposed detector to be implemented in many contemporary M-PSK receivers. The optimal behaviour of the PLL will be shown to hold regardless of the SNR (Signal-to-Noise Ratio) and of the AGC (Automatic Gain Control) circuit behaviour. Moreover, the proposed detector has a simple fixed-point structure that can be feasibly implemented using few hardware resources within contemporary FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits). Finally, operation of the proposed detector under frequency-flat slow signal fading conditions is also discussed. I