Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance

The high bandwidth and power needed to process the data coming from modern high resolution focal plane arrays leads to the necessity for fast and efficient read out and data processing. A system that performs block recognition and image classification with efficiency and low latency is presented. The system is comprised of an analog signal processor that will be integrated into the read out integrated circuit. This enables the capability to read out the focal plane array information and process it completely in the analog domain in a comparably very small amount of operational steps. The steps and techniques of the design flow, including definition of problem, concepts and design of system architecture, simulation of system, and analog lay out practices are covered

Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

A micropower centroiding vision processor

Published versio

Form Factor Improvement of Smart-Pixels for Vision Sensors through 3-D Vertically- Integrated Technologies

While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.Office of Naval Research N000141110312Ministerio de Ciencia e Innovación IPT-2011-1625-43000

A sub-mW IoT-endnode for always-on visual monitoring and smart triggering

This work presents a fully-programmable Internet of Things (IoT) visual sensing node that targets sub-mW power consumption in always-on monitoring scenarios. The system features a spatial-contrast $128\mathrm{x}64$ binary pixel imager with focal-plane processing. The sensor, when working at its lowest power mode ($10\mu W$ at 10 fps), provides as output the number of changed pixels. Based on this information, a dedicated camera interface, implemented on a low-power FPGA, wakes up an ultra-low-power parallel processing unit to extract context-aware visual information. We evaluate the smart sensor on three always-on visual triggering application scenarios. Triggering accuracy comparable to RGB image sensors is achieved at nominal lighting conditions, while consuming an average power between $193\mu W$ and $277\mu W$, depending on context activity. The digital sub-system is extremely flexible, thanks to a fully-programmable digital signal processing engine, but still achieves 19x lower power consumption compared to MCU-based cameras with significantly lower on-board computing capabilities.Comment: 11 pages, 9 figures, submitteted to IEEE IoT Journa

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

Radar systems for the water resources mission, volume 2

The application of synthetic aperture radar (SAR) in monitoring and managing earth resources was examined. The function of spaceborne radar is to provide maps and map imagery to be used for earth resource and oceanographic applications. Spaceborne radar has the capability of mapping the entire United States regardless of inclement weather; however, the imagery must have a high degree of resolution to be meaningful. Attaining this resolution is possible with the SAR system. Imagery of the required quality must first meet mission parameters in the following areas: antenna patterns, azimuth and range ambiguities, coverage, and angle of incidence

A Study of Linear Approximation Techniques for SAR Azimuth Processing

The application of the step transform subarray processing techniques to synthetic aperture radar (SAR) was studied. The subarray technique permits the application of efficient digital transform computational techniques such as the fast Fourier transform to be applied while offering an effective tool for range migration compensation. Range migration compensation is applied at the subarray level, and with the subarray size based on worst case range migration conditions, a minimum control system is achieved. A baseline processor was designed for a four-look SAR system covering approximately 4096 by 4096 SAR sample field every 2.5 seconds. Implementation of the baseline system was projected using advanced low power technologies. A 20 swath is implemented with approximately 1000 circuits having a power dissipation of from 70 to 195 watts. The baseline batch step transform processor is compared to a continuous strip processor, and variations of the baseline are developed for a wide range of SAR parameters