Formal Verification of Probabilistic SystemC Models with Statistical Model Checking

Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have inherent probabilistic behaviors, e.g., random data and unreliable components. It thus is crucial to have both quantitative and qualitative analysis of the probabilities of system properties. Such analysis can be conducted by constructing a formal model of the system under verification and using Probabilistic Model Checking (PMC). However, this method is infeasible for large systems, due to the state space explosion. In this article, we demonstrate the successful use of Statistical Model Checking (SMC) to carry out such analysis directly from large SystemC models and allow designers to express a wide range of useful properties. The first contribution of this work is a framework to verify properties expressed in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and probabilistic characteristics. Second, the framework allows users to expose a rich set of user-code primitives as atomic propositions in BLTL. Moreover, users can define their own fine-grained time resolution rather than the boundary of clock cycles in the SystemC simulation. The third contribution is an implementation of a statistical model checker. It contains an automatic monitor generation for producing execution traces of the model-under-verification (MUV), the mechanism for automatically instrumenting the MUV, and the interaction with statistical model checking algorithms.Comment: Journal of Software: Evolution and Process. Wiley, 2017. arXiv admin note: substantial text overlap with arXiv:1507.0818

An executable semantics of SystemC transaction level models and its applications with VERDS

Transaction level modeling (TLM) is a high-level approach to modeling digital systems where details of communication are separated from the details of computation. In SystemC transaction level models, modules communicate through function calls provided by channels, which include primitive channels and hierarchical channels. This work extends the semantics of simple SystemC models in previous work to support the key concepts of SystemC transaction level models and presents a tool to transform SystemC source codes in TLM-1.0 to transition systems for the purpose of verification on symbolic model checker VERDS. Our approach is demonstrated through a case study of an abstract bus implemented in TLM-1.0 of SystemC.Transaction level modeling (TLM) is a high-level approach to modeling digital systems where details of communication are separated from the details of computation. In SystemC transaction level models, modules communicate through function calls provided by channels, which include primitive channels and hierarchical channels. This work extends the semantics of simple SystemC models in previous work to support the key concepts of SystemC transaction level models and presents a tool to transform SystemC source codes in TLM-1.0 to transition systems for the purpose of verification on symbolic model checker VERDS. Our approach is demonstrated through a case study of an abstract bus implemented in TLM-1.0 of SystemC