A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

THERMAL STRESS MITIGATION OF SINGLE-PHASE SINEWAVE INVERTER BY USING DOUBLE SWITCH H BRIDGE CONFIGURATION

The increasing demand for renewable energies and the ongoing advancement in the industry require continuously evolving power converters in terms of efficiency, power density, and reliability. Furthermore, power converters’ applications in harsh and remote environments such as offshore wind turbines demand robust and reliable designs to help reduce operational costs. Power switch failure is a critical reliability issue that leads to the converter going out of service, causing an unscheduled maintenance event. The main reason behind power switch failure is thermal cycling. Therefore, the first part of this thesis attempts to develop an effective double switch H bridge inverter topology aiming to lessen thermal cycling subjected to power switches, increasing the expected lifetime of power switches, improving the system\u27s overall reliability, and reducing operational costs. Meanwhile, the second focus of the thesis is to develop a visual interpretation of an empirical lifetime estimation model that enables the evaluation of the proposed inverter topology compared to the conventional topology. This is done by producing a novel lifetime improvement evaluation curve based on a common empirical lifetime estimation model using MATLAB®. Moreover, the interpretation of the empirical lifetime estimation models as a lifetime improvement evaluation curve helps to bridge the gap between any thermal condition change and its impact on the expected lifetime. The percentage reduction in the junction’s median temperature %_ and the percentage reduction in the temperature swing %Δ_ are taken as the main contributors to the change in the switch’s estimated cycles to failure . The effectiveness of the proposed topology was verified via simulation of the thermal parameters for the two topologies via PLECS® software. Several test scenarios were performed to illustrate the impact of shifting from the conventional topology to the proposed topology. Following that, numerous loading conditions were considered to perform an extensive comparative analysis between the proposed and the conventional topologies. Three power factor values were adopted at high, medium, and low values; to compare the two topologies while covering an adequate loading range for each power factor value. The assessment indices, namely, Life Prolonging Factor (LPF), and the average LPF (in a temperature range) obtained promising results, especially for high loading levels conditions. The LPF reached values more than ‘2’ under some conditions, indicating a more than double lifetime increase. Furthermore, the average LPF in a specific temperature range indicated promising results in general for common loading conditions with an advantage for higher loading conditions over lower loading conditions

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Autonomous spacecraft maintenance study group

A plan to incorporate autonomous spacecraft maintenance (ASM) capabilities into Air Force spacecraft by 1989 is outlined. It includes the successful operation of the spacecraft without ground operator intervention for extended periods of time. Mechanisms, along with a fault tolerant data processing system (including a nonvolatile backup memory) and an autonomous navigation capability, are needed to replace the routine servicing that is presently performed by the ground system. The state of the art fault handling capabilities of various spacecraft and computers are described, and a set conceptual design requirements needed to achieve ASM is established. Implementations for near term technology development needed for an ASM proof of concept demonstration by 1985, and a research agenda addressing long range academic research for an advanced ASM system for 1990s are established

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

A software controlled voltage tuning system using multi-purpose ring oscillators

This paper presents a novel software driven voltage tuning method that utilises multi-purpose Ring Oscillators (ROs) to provide process variation and environment sensitive energy reductions. The proposed technique enables voltage tuning based on the observed frequency of the ROs, taken as a representation of the device speed and used to estimate a safe minimum operating voltage at a given core frequency. A conservative linear relationship between RO frequency and silicon speed is used to approximate the critical path of the processor. Using a multi-purpose RO not specifically implemented for critical path characterisation is a unique approach to voltage tuning. The parameters governing the relationship between RO and silicon speed are obtained through the testing of a sample of processors from different wafer regions. These parameters can then be used on all devices of that model. The tuning method and software control framework is demonstrated on a sample of XMOS XS1-U8A-64 embedded microprocessors, yielding a dynamic power saving of up to 25% with no performance reduction and no negative impact on the real-time constraints of the embedded software running on the processor

FY2011 Oak Ridge National Laboratory Annual Progress Report for the Power Electronics and Electric Machinery Program

The U.S. Department of Energy (DOE) announced in May 2011 a new cooperative research effort comprising DOE, the U.S. Council for Automotive Research (composed of automakers Ford Motor Company, General Motors Company, and Chrysler Group), Tesla Motors, and representatives of the electric utility and petroleum industries. Known as U.S. DRIVE (Driving Research and Innovation for Vehicle efficiency and Energy sustainability), it represents DOE's commitment to developing public-private partnerships to fund high risk-high reward research into advanced automotive technologies. The new partnership replaces and builds upon the partnership known as FreedomCAR (derived from 'Freedom' and 'Cooperative Automotive Research') that ran from 2002 through 2010 and the Partnership for a New Generation of Vehicles initiative that ran from 1993 through 2001. The Oak Ridge National Laboratory's (ORNL's) Power Electronics and Electric Machines (PEEM) subprogram within the DOE Vehicle Technologies Program (VTP) provides support and guidance for many cutting-edge automotive technologies now under development. Research is focused on developing revolutionary new power electronics (PE), electric motor (EM), and traction drive system technologies that will leapfrog current on-the-road technologies. The research and development (R&D) is also aimed at achieving a greater understanding of and improvements in the way the various new components of tomorrow's automobiles will function as a unified system to improve fuel efficiency. In supporting the development of advanced vehicle propulsion systems, the PEEM subprogram has enabled the development of technologies that will significantly improve efficiency, costs, and fuel economy. The PEEM subprogram supports the efforts of the U.S. DRIVE partnership through a three phase approach intended to: (1) identify overall propulsion and vehicle related needs by analyzing programmatic goals and reviewing industry's recommendations and requirements and then develop the appropriate technical targets for systems, subsystems, and component R&D activities; (2) develop and validate individual subsystems and components, including EMs and PE; and (3) determine how well the components and subsystems work together in a vehicle environment or as a complete propulsion system and whether the efficiency and performance targets at the vehicle level have been achieved. The research performed under this subprogram will help remove technical and cost barriers to enable the development of technology for use in such advanced vehicles as hybrid electric vehicles (HEVs), plug-in HEVs (PHEVs), battery electric vehicles, and fuel-cell-powered automobiles that meet the goals of the VTP. A key element in making these advanced vehicles practical is providing an affordable electric traction drive system. This will require attaining weight, volume, efficiency, and cost targets for the PE and EM subsystems of the traction drive system. Areas of development include: (1) novel traction motor designs that result in increased power density and lower cost; (2) inverter technologies involving new topologies to achieve higher efficiency with the ability to accommodate higher temperature environments while achieving high reliability; (3) converter concepts that use methods of reducing the component count and integrating functionality to decrease size, weight, and cost; (4) new onboard battery charging concepts that result in decreased cost and size; (5) more effective thermal control through innovative packaging technologies; and (6) integrated motor-inverter traction drive system concepts. ORNL's PEEM research program conducts fundamental research, evaluates hardware, and assists in the technical direction of the VTP Advanced Power Electronics and Electric Motors (APEEM) program. In this role, ORNL serves on the U.S. DRIVE Electrical and Electronics Technical Team, evaluates proposals for DOE, and lends its technological expertise to the direction of projects and evaluation of developing technologies. ORNL also executes specific projects for DOE. DOE's continuing R&D into advanced vehicle technologies for transportation offers the possibility of reducing the nation's dependence on foreign oil and the negative economic impacts of crude oil price fluctuations. It also supports the Administration's goal of deploying 1 million PHEVs by 2015

Advanced flight control system study

The architecture, requirements, and system elements of an ultrareliable, advanced flight control system are described. The basic criteria are functional reliability of 10 to the minus 10 power/hour of flight and only 6 month scheduled maintenance. A distributed system architecture is described, including a multiplexed communication system, reliable bus controller, the use of skewed sensor arrays, and actuator interfaces. Test bed and flight evaluation program are proposed