2 research outputs found
Dynamic Power Management for Neuromorphic Many-Core Systems
This work presents a dynamic power management architecture for neuromorphic
many core systems such as SpiNNaker. A fast dynamic voltage and frequency
scaling (DVFS) technique is presented which allows the processing elements (PE)
to change their supply voltage and clock frequency individually and
autonomously within less than 100 ns. This is employed by the neuromorphic
simulation software flow, which defines the performance level (PL) of the PE
based on the actual workload within each simulation cycle. A test chip in 28 nm
SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled
from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct
PLs. By measurement of three neuromorphic benchmarks it is shown that the total
PE power consumption can be reduced by 75%, with 80% baseline power reduction
and a 50% reduction of energy per neuron and synapse computation, all while
maintaining temporary peak system performance to achieve biological real-time
operation of the system. A numerical model of this power management model is
derived which allows DVFS architecture exploration for neuromorphics. The
proposed technique is to be used for the second generation SpiNNaker
neuromorphic many core system
μ°¨μΈλ HBM μ© κ³ μ§μ , μ μ λ ₯ μ‘μμ κΈ° μ€κ³
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Όλ¬Έ (λ°μ¬) -- μμΈλνκ΅ λνμ : 곡과λν μ κΈ°Β·μ 보곡νλΆ, 2020. 8. μ λκ· .This thesis presents design techniques for high-density power-efficient transceiver for the next-generation high bandwidth memory (HBM). Unlike the other memory interfaces, HBM uses a 3D-stacked package using through-silicon via (TSV) and a silicon interposer. The transceiver for HBM should be able to solve the problems caused by the 3D-stacked package and TSV.
At first, a data (DQ) receiver for HBM with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift is proposed. The self-tracking loop achieves low power and small area by uti-lizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage differ-ence and detects the phase skew from the voltage difference. An offset calibra-tion scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing cir-cuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver op-erates without any performance degradation under a Β± 10% supply variation.
In a second prototype IC, a high-density transceiver for HBM with a feed-forward-equalizer (FFE)-combined crosstalk (XT) cancellation scheme is pre-sented. To compensate for the XT, the transmitter pre-distorts the amplitude of the FFE output according to the XT. Since the proposed XT cancellation (XTC) scheme reuses the FFE implemented to equalize the channel loss, additional circuits for the XTC is minimized. Thanks to the XTC scheme, a channel pitch can be significantly reduced, allowing for the high channel density. Moreover, the 3D-staggered channel structure removes the ground layer between the verti-cally adjacent channels, which further reduces a cross-sectional area of the channel per lane. The test chip including 6 data lanes is fabricated in 65 nm CMOS technology. The 6-mm channels are implemented on chip to emulate the silicon interposer between the HBM and the processor. The operation of the XTC scheme is verified by simultaneously transmitting 4-Gb/s data to the 6 consecutive channels with 0.5-um pitch and the XTC scheme reduces the XT-induced jitter up to 78 %. The measurement result shows that the transceiver achieves the throughput of 8 Gb/s/um. The transceiver occupies 0.05 mm2 for 6 lanes and consumes 36.6 mW at 6 x 4 Gb/s.λ³Έ λ
Όλ¬Έμμλ μ°¨μΈλ HBMμ μν κ³ μ§μ μ μ λ ₯ μ‘μμ κΈ° μ€κ³ λ°©λ²μ μ μνλ€. 첫 λ²μ§Έλ‘, μ μ λ° μ¨λ λ³νμ μν λ°μ΄ν°μ ν΄λ κ° μμ μ°¨μ΄λ₯Ό 보μν μ μλ μ체 μΆμ 루νλ₯Ό κ°μ§ λ°μ΄ν° μμ κΈ°λ₯Ό μ μνλ€. μ μνλ μ체 μΆμ 루νλ λ°μ΄ν° μ μ‘ μλμ κ°μ μλλ‘ λμνλ μμ κ²μΆκΈ°λ₯Ό μ¬μ©νμ¬ μ λ ₯ μλͺ¨μ λ©΄μ μ μ€μλ€. λν λ©λͺ¨λ¦¬μ μ°κΈ° νλ ¨ (write training) κ³Όμ μ μ΄μ©νμ¬ ν¨κ³Όμ μΌλ‘ μμ κ²μΆκΈ°μ μ€νμ
μ 보μν μ μλ λ°©λ²μ μ μνλ€. μ μνλ λ°μ΄ν° μμ κΈ°λ 65 nm 곡μ μΌλ‘ μ μλμ΄ 4.8 Gb/sμμ 370 fJ/bμ μλͺ¨νμλ€. λν 10 % μ μ μ λ³νμ λνμ¬ μμ μ μΌλ‘ λμνλ κ²μ νμΈνμλ€.
λ λ²μ§Έλ‘, νΌλ ν¬μλ μ΄νλΌμ΄μ μ κ²°ν©λ ν¬λ‘μ€ ν ν¬ λ³΄μ λ°©μμ νμ©ν κ³ μ§μ μ‘μμ κΈ°λ₯Ό μ μνλ€. μ μνλ μ‘μ κΈ°λ ν¬λ‘μ€ ν ν¬ ν¬κΈ°μ ν΄λΉνλ λ§νΌ μ‘μ κΈ° μΆλ ₯μ μ곑νμ¬ ν¬λ‘μ€ ν ν¬λ₯Ό 보μνλ€. μ μνλ ν¬λ‘μ€ ν ν¬ λ³΄μ λ°©μμ μ±λ μμ€μ 보μνκΈ° μν΄ κ΅¬νλ νΌλ ν¬μλ μ΄νλΌμ΄μ λ₯Ό μ¬νμ©ν¨μΌλ‘μ¨ μΆκ°μ μΈ νλ‘λ₯Ό μ΅μννλ€. μ μνλ μ‘μμ κΈ°λ ν¬λ‘μ€ ν ν¬κ° 보μ κ°λ₯νκΈ° λλ¬Έμ, μ±λ κ°κ²©μ ν¬κ² μ€μ¬ κ³ μ§μ ν΅μ μ ꡬννμλ€. λν μ§μ λλ₯Ό λ μ¦κ°μν€κΈ° μν΄ μΈλ‘λ‘ μΈμ ν μ±λ μ¬μ΄μ μ°¨ν μΈ΅μ μ κ±°ν μ μΈ΅ μ±λ ꡬ쑰λ₯Ό μ μνλ€. 6κ°μ μ‘μμ κΈ°λ₯Ό ν¬ν¨ν νλ‘ν νμ
μΉ©μ 65 nm 곡μ μΌλ‘ μ μλμλ€. HBMκ³Ό νλ‘μΈμ μ¬μ΄μ silicon interposer channel μ λͺ¨μ¬νκΈ° μν 6 mm μ μ±λμ΄ μΉ© μμ ꡬνλμλ€. μ μνλ ν¬λ‘μ€ ν ν¬ λ³΄μ λ°©μμ 0.5 um κ°κ²©μ 6κ°μ μΈμ ν μ±λμ λμμ λ°μ΄ν°λ₯Ό μ μ‘νμ¬ κ²μ¦λμμΌλ©°, ν¬λ‘μ€ ν ν¬λ‘ μΈν μ§ν°λ₯Ό μ΅λ 78 % κ°μμμΌ°λ€. μ μνλ μ‘μμ κΈ°λ 8 Gb/s/um μ μ²λ¦¬λμ κ°μ§λ©° 6 κ°μ μ‘μμ κΈ°κ° μ΄ 36.6 mWμ μ λ ₯μ μλͺ¨νμλ€.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 4
CHAPTER 2 BACKGROUND ON HIGH-BANDWIDTH MEMORY 6
2.1 OVERVIEW 6
2.2 TRANSCEIVER ARCHITECTURE 10
2.3 READ/WRITE OPERATION 15
2.3.1 READ OPERATION 15
2.3.2 WRITE OPERATION 19
CHAPTER 3 BACKGROUNDS ON COUPLED WIRES 21
3.1 GENERALIZED MODEL 21
3.2 EFFECT OF CROSSTALK 26
CHAPTER 4 DQ RECEIVER WITH BAUD-RATE SELF-TRACKING LOOP 29
4.1 OVERVIEW 29
4.2 FEATURES OF DQ RECEIVER FOR HBM 33
4.3 PROPOSED PULSE-TO-CHARGE PHASE DETECTOR 35
4.3.1 OPERATION OF PULSE-TO-CHARGE PHASE DETECTOR 35
4.3.2 OFFSET CALIBRATION 37
4.3.3 OPERATION SEQUENCE 39
4.4 CIRCUIT IMPLEMENTATION 42
4.5 MEASUREMENT RESULT 46
CHAPTER 5 HIGH-DENSITY TRANSCEIVER FOR HBM WITH 3D-STAGGERED CHANNEL AND CROSSTALK CANCELLATION SCHEME 57
5.1 OVERVIEW 57
5.2 PROPOSED 3D-STAGGERED CHANNEL 61
5.2.1 IMPLEMENTATION OF 3D-STAGGERED CHANNEL 61
5.2.2 CHANNEL CHARACTERISTICS AND MODELING 66
5.3 PROPOSED FEED-FORWARD-EQUALIZER-COMBINED CROSSTALK CANCELLATION SCHEME 72
5.4 CIRCUIT IMPLEMENTATION 77
5.4.1 OVERALL ARCHITECTURE 77
5.4.2 TRANSMITTER WITH FFE-COMBINED XTC 79
5.4.3 RECEIVER 81
5.5 MEASUREMENT RESULT 82
CHAPTER 6 CONCLUSION 93
BIBLIOGRAPHY 95
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