A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation.2011 Asian Test Symposium (ATS), 20-23 Nov. 2011, New Delhi, Indi

Built-in self-test and self-calibration for analog and mixed signal circuits

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. This dissertation introduces two ADC testing algorithms and two ADC built-in self-test circuit implementations to test the ADC integral nonlinearity (INL) and differential nonlinearity (DNL) on-chip. In the first testing algorithm, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) is developed for ADC built-in self-test, which eliminates the need for precision stimulus and reduces the overall test time. In this algorithm, the ADC is tested twice with a nonlinear ramp, instead of using a linear ramp signal. Therefore, the stimulus can be easily generated on-chip in a low-cost way. For the two ramps, there is a constant voltage shift in between. As the input stimulus linearity is completely relaxed, there is no requirement on the waveform of the input stimulus as long as it covers the ADC input range. In the meantime, the high-resolution ADC linearity is modeled with segmented parameters, which reduces the number of samples required for achieving high-precision test, thus saving the test time. As a result, the USER-SMILE algorithm is able to use less than 1 sample/code nonlinear stimulus to test high resolution ADCs with less than 0.5 least significant bit (LSB) INL estimation error, achieving more than 10-time test time reduction. This algorithm is validated with both board-level implementation and on-chip silicon implementation. The second testing algorithm is proposed to test the INL/DNL for multi-bit-per-stages pipelined ADCs with reduced test time and better test coverage. Due to the redundancy characteristics of multi-bit-per-stages pipelined ADC, the conventional histogram test cannot estimate and calibrate the static linearity accurately. The proposed method models the pipelined ADC nonlinearity as segmented parameters with inter-stage gain errors using the raw codes instead of the final output codes. During the test phase, a pure sine wave is sent to the ADC as the input and the model parameters are estimated from the output data with the system identification method. The modeled errors are then removed from the digital output codes during the calibration phase. A high-speed 12-bit pipelined ADC is tested and calibrated with the proposed method. With only 4000 samples, the 12-bit ADC is accurately tested and calibrated to achieve less than 1 LSB INL. The ADC effective number of bits (ENOB) is improved from 9.7 bits to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by more than 20dB after calibration. In the first circuit implementation, a low-cost on-chip built-in self-test solution is developed using an R2R digital-to-analog converter (DAC) structure as the signal generator and the voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by mismatches, which relaxes the DAC matching requirements and reduces the design area. The R2R DAC based BIST circuit is fabricated in TSMC 40nm technology with a small area of 0.02mm^2. Measurement results show that the BIST circuit is capable of testing a 15-bit ADC INL accurately with less than 0.5 LSB INL estimation error. In the second circuit implementation, a complete SAR ADC built-in self-test solution using the USER-SMILE is developed and implemented in a 28nm automotive microcontroller. A low-cost 12-bit resistive DAC with less than 12-bit linearity is used as the signal generator to test and calibrate a SAR ADC with a target linearity of 12 bits. The voltage shift generation is created inside the ADC with capacitor switching. The entire algorithm processing unit for USER-SMILE algorithm is also implemented on chip. The final testing results are saved in the memory for further digital calibration. Both the total harmonic distortion (THD) and the SFDR are improved by 20dB after calibration, achieving -84.5dB and 86.5dB respectively. More than 700 parts are tested to verify the robustness of the BIST solution

Analysis and application of digital spectral warping in analog and mixed-signal testing

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Built-in-self-test of RF front-end circuitry

Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults. Due to the absence of contact based testing solutions in embedded RF SOCs (because the very act of probing may affect the performance of the RF circuit), coupled with the presence of very few test access nodes, a Built In Self Test approach (BiST) may prove to be the most efficient test scheme. However due to the associated challenges, a comprehensive and low-overhead BiST methodology for on-chip testing of RF ICs has not yet been reported in literature. In the current work, an approach to RF self-test that has hitherto been unexplored both in literature and in the commercial arena is proposed. A sensitive current monitor has been used to extract variations in the supply current drawn by the circuit-under-test (CUT). These variations are then processed in time and frequency domain to develop signatures. The acquired signatures can then be mapped to specific behavioral anomalies and the locations of these anomalies. The CUT is first excited by simple test inputs that can be generated on-chip. The current monitor extracts the corresponding variations in the supply current of the CUT, thereby creating signatures that map to various performance metrics of the circuit. These signatures can then be post-processed by low overhead on-chip circuitry and converted into an accessible form. To be successful in the RF domain any BIST architecture must be minimally invasive, reliable, offer good fault coverage and present low real estate and power overheads. The current-based self-test approach successfully addresses all these concerns. The technique has been applied to RF Low Noise Amplifiers, Mixers and Voltage Controlled Oscillators. The circuitry and post-processing techniques have also been demonstrated in silicon (using the IBM 0.25 micron RF CMOS process). The entire self-test of the RF front-end can be accomplished with a total test time of approximately 30µs, which is several orders of magnitude better than existing commercial test schemes