An automated meta-level control framework for optimizing the quality-time tradeoff of VLSI algorithms

We address the problem of optimizing the quality-time tradeoff of very large scale integration (VLSI) computer-aided design (CAD) algorithms working under various constrained environments. We present a unified meta-reasoning framework to automatically control the progress of iteratively improving CAD algorithms. The control framework uses profile knowledge about the quality-time relation of the algorithms used and generates a combined strategy for time allocation and parameter control that optimizes the expected tradeoff. We present specific formulations for handling single and multiple problems (both dependent and independent) under various constraints. We use the proposed strategies for adjusting the control parameters of standard simulated annealing and genetic algorithm based techniques used in VLSI optimization along with an appropriate time allocation suited for different constraint specifications. Application on several classical problems in the VLSI domain shows that significant improvement in quality-time tradeoff can be achieved