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7 research outputs found

An efficient graph representation for arithmetic circuit verification

Author: R.E. Bryant
Yirng-An Chen
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date
Field of study

Mapping switch-level simulation onto gate-level hardware accelerators

Author: Alok Jain (5415110)
Randal E. Bryant (5409038)
Publication venue: 'Association for Computing Machinery (ACM)'
Publication date: 01/01/1991
Field of study

In this paper, we present a framework for performing switch-level simulation on hardware accelerators

*PHDD: an efficient graph representation for floating point circuit verification

Author
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date: 01/01/1997
Field of study

Formal verification of an ARM processor

Author
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date: 01/01/1999
Field of study

Formal verification by symbolic evaluation of partially-ordered trajectories

Author: Carl-Johan H. Seger
D. S. Reeves
E. M. Clarke
J. A. Brzozowski
J. S. Jephson
N. Halbwachs
R. E. Bryant
R. E. Bryant
R. E. Bryant
R. E. Bryant
R. E. Bryant
R. E. Bryant
R. P. Kurshan
Randal E. Bryant
Publication venue: 'Springer Science and Business Media LLC'
Publication date
Field of study

A Methodology for Hardware Verification Based on Logic Simulation.

Author
Publication venue: 'Defense Technical Information Center (DTIC)'
Publication date
Field of study

An Analysis of Hashing on Parallel and Vector Computers

Author
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date
Field of study

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