An Accelerator for Double Precision Floating Point Operations

We describe DPFPA (Double Precision Floating Point Accelerator) an FPGA based coprocessor interfaced to the CPU through the PCI bus; it is conceived to accelerate the evaluation of double precision floating point operations. This coprocessor is based on two double precision floating point units: a pipelined adder and a pipelined multiplier. The work is part of a global project aimed to design and build a parallel system made up by a cluster of accelerated workstations. First estimations of performance have been obtained, using a similar board developed at Fermilab (Batavia, IL) with less recent components and working at half the frequency with respect to DPFPA. Even in this case, a substantial acceleration with respect to the execution on Intel’s CPU based mother-board was observed

An accelerator for double precision floating point operations

We describe DPFPA (Double Precision Floating Point Accelerator) an FPGA based coprocessor interfaced to the CPU through the PCI bus; it is conceived to accelerate the evaluation of double precision floating point operations. This coprocessor is based on two double precision floating point units: a pipelined adder and a pipelined multiplier. The work is part of a global project aimed to design and build a parallel system made up by a cluster of accelerated workstations. First estimations of performance have been obtained, using a similar board developed at Fermilab (Batavia, IL) with less recent components and working at half the frequency with respect to DPFPA. Even in this case, a substantial acceleration with respect to the execution on Intel’s CPU based mother-board was observed