504 research outputs found
Design and qualification of the SEU/TD Radiation Monitor chip
This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL
Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting in voltage and current perturbation, where errors are induced. This phenomenon is termed a Single Event Effect (SEE). With the shrinking of transistor size, charge sharing between adjacent devices leads to less effectiveness of current radiation hardening methods. Improving fault-tolerance of storage cells and logic gates in advanced technologies becomes urgent and important.
A new Single Event Upset (SEU) tolerant latch is proposed based on a previous hardened Quatro design. Soft error analysis tools are used and results show that the critical charge of the proposed design is approximately 2 times higher than that of the reference design with negligible penalty in area, delay, and power consumption. A test chip containing the proposed flip-flop chains was designed and exposed to alpha particles as well as heavy ions. Radiation experimental results indicate that the soft error rates of the proposed design are greatly reduced when Linear Energy Transfer (LET) is lower than 4, which makes it a suitable candidate for ground-level high reliability applications.
To improve radiation tolerance of combinational circuits, two combinational logic gates are proposed. One is a layout-based hardening Cascode Voltage Switch Logic (CVSL) and the other is a fault-tolerant differential dynamic logic. Results from a SEE simulation tool indicate that the proposed CVSL has a higher critical charge, less cross section, and shorter Single Event Transient (SET) pulses when compared with reference designs. Simulation results also reveal that the proposed differential dynamic logic significantly reduces the SEU rate compared to traditional dynamic logic, and has a higher critical charge and shorter SET pulses than reference hardened design
Effects of cosmic rays on single event upsets
The efforts at establishing a research program in space radiation effects are discussed. The research program has served as the basis for training several graduate students in an area of research that is of importance to NASA. In addition, technical support was provided for the Single Event Facility Group at Brookhaven National Laboratory
Soft-Error Rate of Advanced SRAM Memories: Modeling and Monte Carlo Simulation
International audienc
STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS
Microelectronic devices and systems have been extensively utilized in a variety of radiation
environments, ranging from the low-earth orbit to the ground level. A high-energy particle from
such an environment may cause voltage/current transients, thereby inducing Single Event Effect
(SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975,
this community has made tremendous progress in investigating the mechanisms of SEE and
exploring radiation tolerant techniques. However, as the IC technology advances, the existing
hardening techniques have been rendered less effective because of the reduced spacing and
charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has
identified radiation-induced soft errors as the major threat to the reliable operation of electronic
systems in the future. In digital systems, hardening techniques of their core components, such as
latches, logic, and clock network, need to be addressed.
Two single event tolerant latch designs taking advantage of feedback transistors are
presented and evaluated in both single event resilience and overhead. These feedback transistors
are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in
a larger feedback delay and higher single event tolerance. On the other hand, these extra
transistors are turned ON when the cell is in the write mode. As a result, no significant write
delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section
when compared to the reference cells.
Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The
worst case occurs when the output is evaluated logic high, where the pull-up networks are turned
OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail.
A capacitor added to the feedback path increases the node capacitance of the output and the
feedback delay, thereby increasing the single event critical charge. Another differential structure
that has two differential inputs and outputs eliminates single event upset issues at the expense of
an increased number of transistors.
Clock networks in advanced technology nodes may cause significant errors in an IC as the
devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme
in a digital system. It was fabricated in a 28nm technology and evaluated through the use of
heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was
demonstrated during these tests.
In addition to mitigating single event issues by using hardened designs, built-in current
sensors can be used to detect single event induced currents in the n-well and, if implemented,
subsequently execute fault correction actions. These sensors were simulated and fabricated in a
28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of
this sensor design. This manifests itself as an alternative to existing hardening techniques.
In conclusion, this work investigates single event effects in digital systems, especially those
in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock,
and current sensor designs have been presented and evaluated. Through the use of these designs,
the single event tolerance of a digital system can be achieved at the expense of varying overhead
in terms of area, power, and delay
Effects of cosmic rays on single event upsets
Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested
Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets
Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction
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