Aliasing Probability Calculations In Nonlinear Compactors

This paper discusses a systematic methodology for calculating the aliasing probability when an arbitrary finite-state machine is used to compact the response of a combinational circuit to a sequence of randomly generated test input vectors. The proposed approach is general and is based on simultaneously tracking the states of two (fictitious) compactors, one driven by the response of the fault-free combinational circuit and the other one driven by the response of the faulty combinational circuit. By deriving the overall Markov chain that describes the combined behavior of these two compactors, we are able to calculate the exact aliasing probability based on its stationary distribution and to demonstrate regimes over which nonlinear compactors may be preferable over linear compactors