11,323 research outputs found
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories
In this paper we study Complex Read Faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic faults concerning this operation. The requirements to cover these fault models are given. We show that the different causes of read failure are independent and may coexist in nanoscale SRAMs, summing their effects and provoking Complex Read Faults, CRFs. We show that the test methodology to cover this new read faults consists in test patterns that match the requirements to cover all the different simple read fault models. We propose a low complexity (?2N) test, March CRF, that covers effectively all the realistic Complex Read Fault
On applying the set covering model to reseeding
The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits. To date, however, we have not found any work that aims at protecting the control logic of these circuits against fault attacks, which thus remains the proverbial Achilles’ heel. Motivated by a hypothetical yet realistic fault analysis attack that, in principle, could be mounted against any modular exponentiation engine, even one with appropriate data path protection, we set out to close this remaining gap. In this paper, we present guidelines for the design of multifault-resilient sequential control logic based on standard Error-Detecting Codes (EDCs) with large minimum distance. We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in
implementing the EDC. Our comparison shows that the proposed EDC-based technique provides superior performance when compared against regular N-modular redundancy techniques. Furthermore, our technique scales well and does not affect the critical path delay
Fault Models for Quantum Mechanical Switching Networks
The difference between faults and errors is that, unlike faults, errors can
be corrected using control codes. In classical test and verification one
develops a test set separating a correct circuit from a circuit containing any
considered fault. Classical faults are modelled at the logical level by fault
models that act on classical states. The stuck fault model, thought of as a
lead connected to a power rail or to a ground, is most typically considered. A
classical test set complete for the stuck fault model propagates both binary
basis states, 0 and 1, through all nodes in a network and is known to detect
many physical faults. A classical test set complete for the stuck fault model
allows all circuit nodes to be completely tested and verifies the function of
many gates. It is natural to ask if one may adapt any of the known classical
methods to test quantum circuits. Of course, classical fault models do not
capture all the logical failures found in quantum circuits. The first obstacle
faced when using methods from classical test is developing a set of realistic
quantum-logical fault models. Developing fault models to abstract the test
problem away from the device level motivated our study. Several results are
established. First, we describe typical modes of failure present in the
physical design of quantum circuits. From this we develop fault models for
quantum binary circuits that enable testing at the logical level. The
application of these fault models is shown by adapting the classical test set
generation technique known as constructing a fault table to generate quantum
test sets. A test set developed using this method is shown to detect each of
the considered faults.Comment: (almost) Forgotten rewrite from 200
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