Algorithms for scheduling of data transfer across FPGAs in a grid

The problem of scheduling data transfer across FPGA chips arranged in a grid arises in the design of Simulation Accelerators and Emulators. Data (collection of bits) are to be transferred across specified pairs of FPGAs in as few clock cycles as possible, subject to the link capacities of the grid and other constraints. We have devised and implemented a greedy algorithm for the problem and experimentally tested the same. The algorithm could always compute schedules with clock cycle requirement within twice the optimal value for grids of size upto 32 x 32 (state of the art) and large number of demands. We also developed other approaches that make use of linear programming and rounding techniques to find paths for the data transfer An actual schedule using these paths can then be computed using three different approaches, two Of the which give constant factor approximation in terms of the clock cycles needed to transfer data using only "one-bend" shortest paths, with intermediate buffering allowed