Advanced modeling of planarization processes for integrated circuit fabrication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 215-225).Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted.by Wei Fan.Ph.D

Micro-scale scratching by soft pad asperities in chemical-mechanical polishing

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2013.Cataloged from PDF version of thesis.Includes bibliographical references.In the manufacture of integrated circuits (IC) and micro-electromechanical systems (MEMS), chemical-mechanical polishing (CMP) is widely used for providing local and global planarization. In the CMP process, polishing pads, typically made of polyurethanes, play a key role. Due to the random, rough surface of the pad, only the tall asperities contact the wafer and transmit the necessary down force and motion to the abrasive particles for material removal. As the applied pressure is concentrated under few asperities, however, the asperities themselves, even though softer, may generate unintended micro-scratches on relatively hard surfaces under certain conditions. This thesis investigates the effects of topographical, mechanical, and tribological properties of the pad and of the wafer surfaces on pad scratching in CMP. The generation and probability of scratching by soft pad asperities on hard monolithic layers are modeled. At single-asperity sliding contact, the asperity contact pressure along with the interfacial friction that can induce surface layer yielding are first derived, for different asperity deformation modes: elastic, elastic but at the onset of yielding, elastic-plastic, and fully-plastic. Under multi-asperity sliding contact, the probability of scratching asperities is determined taking into account the asperity height variation of the rough pad surface. The models are further advanced for scratching of patterned Cu/dielectric layers. As a result, the conditions for and probability of scratching are presented in terms of the asperity-to-layer hardness ratio, friction coefficient, asperity modulus-hardness ratio and ratio of asperity radius to standard deviation of asperity heights. The scratching models are validated by performing sliding experiments using solid polymer pins and CMP pads. For scratch mitigation, especially, a novel, cost-effective asperity-flattening method is introduced to control the pad topography, i.e., to increase the ratio of asperity radius to standard deviation of asperity heights. Finally, the role of asperities in material removal is studied based on contact mechanics and abrasive wear models. A new material removal rate model is developed in terms of pad surface properties, and polishing experiments are conducted on Cu to validate the theoretical prediction that the asperity-flattened pads not only reduce the pad scratching but also improve the material removal rate.by Sanha Kim.Ph. D