Amélioration du processus de vérification des architectures générées à l'aide d'outils de synthèse de haut-niveau

L'augmentation de la capacité d'intégration des circuits a permis le développement des systèmes de plus en plus complexes. De cette complexité sont nés des besoins conséquents quant aux méthodes de conception et de vérification. Les outils de synthèse de haut-niveau (HLS) sont une des réponses à ces besoins. Les travaux présentés dans cette thèse ont pour cadre l'amélioration du processus de vérification des architectures matérielles synthétisées par HLS. En particulier, ils proposent une méthode pour la transformation des assertions booléennes spécifiées dans la description algorithmique d'une application en moniteurs matériels pour la simulation. Une deuxième méthode est proposée. Elle cible la synthèse automatique d'un gestionnaire d'erreurs matériel dont le rôle est d'archiver les erreurs survenant dans un circuit en fonctionnement réel, ainsi que leurs contextes d'exécution.The fast growing complexity of hardware circuits, during the last three decades, has change devery step of their development cycle. Design methods evolved a lot, and this evolutionwas necessary to cope with an always shorter time-to-market, mainly driven by the internationalcompetition.An increased complexity also means more errors, harder to find corner-cases, and morelong and expensive simulations. The verification of hardware systems requires more andmore resources, and is the main cost factor of the whole development of a circuit. Since thecomplexity of any system increases, the cost of an error undetected until the foundry stepbecame prohibitive. Therefore, the verification process is divided between multiple stepsinvolved at every moment of the design process : comparison of models behavior, simulationof RTL descriptions, formal analysis of algorithms, assertions usage, etc. The verificationmethodologies evolved a lot, in order to follow the progress of design methods. Somemethods like the Assertion-Based Verification became so important that they are nowwidely adopted among the developers community, providing near-source error detection.Thus, the work described here aims at improving the assertion-based verification process,in order to offer a consequent timing improvment to designers. Two contributions aredetailed. The first one deals with the transformation of Boolean assertions found in algorithmicdescriptions into equivalent temporal assertions in the RTL description generatedby high-level synthesis (HLS) methodologies. Therefore, the assertions are usable duringthe simulation process of the generated architectures. The second contribution targets theverification of hardware systems in real-time. It details the synthesis process of a hardwareerror manager, which has to save and serialize the execution context when an error isdetected. Thus, it is easier to understand the cause of an error and to find its source. Theerrors and their contexts are serialized as reports in a memory readable by the system ordirectly by the designer. The behavior of a circuit can be analyzed without requiring anyprobe or integrated logic analyzer.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.

Today, design verification is by far the most resource and time-consuming activity of any new digital integrated circuit development. Within this area, the vast majority of the verification effort in industry relies on simulation platforms, which are implemented either in hardware or software. A "simulator" includes a model of each component of a design and has the capability of simulating its behavior under any input scenario provided by an engineer. Thus, simulators are deployed to evaluate the behavior of a design under as many input scenarios as possible and to identify and debug all incorrect functionality. Two features are critical in simulators for the validation effort to be effective: performance and checking/debugging capabilities. A wide range of simulator platforms are available today: on one end of the spectrum there are software-based simulators, providing a very rich software infrastructure for checking and debugging the design's functionality, but executing only at 1-10 simulation cycles per second (while actual chips operate at GHz speeds). At the other end of the spectrum, there are hardware-based platforms, such as accelerators, emulators and even prototype silicon chips, providing higher performances by 4 to 9 orders of magnitude, at the cost of very limited or non-existent checking/debugging capabilities. As a result, today, simulation-based validation is crippled: one can either have satisfactory performance on hardware-accelerated platforms or critical infrastructures for checking/debugging on software simulators, but not both. This dissertation brings together these two ends of the spectrum by presenting solutions that offer high-performance simulation with effective checking and debugging capabilities. Specifically, it addresses the performance challenge of software simulators by leveraging inexpensive off-the-shelf graphics processors as massively parallel execution substrates, and then exposing the parallelism inherent in the design model to that architecture. For hardware-based platforms, the dissertation provides solutions that offer enhanced checking and debugging capabilities by abstracting the relevant data to be logged during simulation so to minimize the cost of collection, transfer and processing. Altogether, the contribution of this dissertation has the potential to solve the challenge of digital design verification by enabling effective high-performance simulation-based validation.PHDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/99781/1/dchatt_1.pd