Power Converter of Electric Machines, Renewable Energy Systems, and Transportation

Power converters and electric machines represent essential components in all fields of electrical engineering. In fact, we are heading towards a future where energy will be more and more electrical: electrical vehicles, electrical motors, renewables, storage systems are now widespread. The ongoing energy transition poses new challenges for interfacing and integrating different power systems. The constraints of space, weight, reliability, performance, and autonomy for the electric system have increased the attention of scientific research in order to find more and more appropriate technological solutions. In this context, power converters and electric machines assume a key role in enabling higher performance of electrical power conversion. Consequently, the design and control of power converters and electric machines shall be developed accordingly to the requirements of the specific application, thus leading to more specialized solutions, with the aim of enhancing the reliability, fault tolerance, and flexibility of the next generation power systems

Some communication algorithms for Gaussian and Eisenstein-Jacobi networks

Interconnection networks play important roles in designing high performance computers. Recently two new classes of interconnection networks based on the concept of Gaussian and Eisenstein-Jacobi integers were introduced. In this research, efficient routing and broadcasting algorithms for these networks are developed. Furthermore, constructing edge disjoint Hamiltonian cycles in Gaussian networks are also investigated. Some resource placement methods for Eisenstein-Jacobi networks are also studied

Memory hierarchy and data communication in heterogeneous reconfigurable SoCs

The miniaturization race in the hardware industry aiming at continuous increasing of transistor density on a die does not bring respective application performance improvements any more. One of the most promising alternatives is to exploit a heterogeneous nature of common applications in hardware. Supported by reconfigurable computation, which has already proved its efficiency in accelerating data intensive applications, this concept promises a breakthrough in contemporary technology development. Memory organization in such heterogeneous reconfigurable architectures becomes very critical. Two primary aspects introduce a sophisticated trade-off. On the one hand, a memory subsystem should provide well organized distributed data structure and guarantee the required data bandwidth. On the other hand, it should hide the heterogeneous hardware structure from the end-user, in order to support feasible high-level programmability of the system. This thesis work explores the heterogeneous reconfigurable hardware architectures and presents possible solutions to cope the problem of memory organization and data structure. By the example of the MORPHEUS heterogeneous platform, the discussion follows the complete design cycle, starting from decision making and justification, until hardware realization. Particular emphasis is made on the methods to support high system performance, meet application requirements, and provide a user-friendly programmer interface. As a result, the research introduces a complete heterogeneous platform enhanced with a hierarchical memory organization, which copes with its task by means of separating computation from communication, providing reconfigurable engines with computation and configuration data, and unification of heterogeneous computational devices using local storage buffers. It is distinguished from the related solutions by distributed data-flow organization, specifically engineered mechanisms to operate with data on local domains, particular communication infrastructure based on Network-on-Chip, and thorough methods to prevent computation and communication stalls. In addition, a novel advanced technique to accelerate memory access was developed and implemented

Design of antenna array and data streaming platform for low-cost smart antenna systems

The wide range of wireless infrastructures such as cellular base stations, wireless hotspots, roadside infrastructures, and wireless mobile infrastructures have been increasing rapidly over the past decades. In the transportation sector, wireless technology refreshes require constantly introducing newer wireless standards into the existing wireless infrastructure. Different wireless standards are expected to co-exist, and the air space congestion worsens if the wireless devices are operating in different wireless standards, where collision avoidance and transmission time synchronisation become complex and almost impossible. Huge challenges are expected such as operation constraints, cross-system interference, and air space congestion. Future proof and scalable smart wireless infrastructures are crucial to harmonise the un-coordinated wireless infrastructures and improve the performance, reliability, and availably of the wireless networks. This thesis presents the detailed design of a novel pre-configurable smart antenna system and its sub-system including antenna element, antenna array, and radio frequency (RF) frontend. Three types of 90° beamforming antenna array (with low, middle and high gain) were designed, simulated, and experimentally evaluated. The RF frontend module or transmit and receive (T/R) module was designed and fabricated. The performance of the T/R module was characterised and calibrated using the recursive calibration method, and drastic sidelobe level (SLL) improvement was achieved using the amplitude distribution technique. Finally, the antenna arrays and T/R modules are integrated into the pre-configurable smart antenna system, the beam steering performance is experimentally evaluated and presented in this thesis. With the combination of practical know-how and theoretical estimation, the thesis highlights how the modern smart antenna techniques that support most cutting-edge wireless technology can be adopted into the existing infrastructure with minimum distraction to the existing systems. This is in line with the global Smart City initiative, where a huge number of Internet of Things (IoT) devices being wired, or wireless are expected to work harmoniously in the same premises. The concept of the pre-configurable smart antenna system presented in this thesis is set to deliver a future-proof and highly scalable and sustainable infrastructure in the transportation market

CMOS system for high throughput fluorescence lifetime sensing using time correlated single photon counting

Fluorescence lifetime sensing using time correlated single photon counting (TCSPC) is a key analytical tool for molecular and cell biology research, medical diagnosis and pharmacological development. However, commercially available TCSPC equipment is bulky, expensive and power hungry, typically requiring iterative software post-processing to calculate the fluorescence lifetime. Furthermore, the technique is restrictively slow due to a low photon throughput limit which is necessary to avoid distortions caused by TCSPC pile-up. An investigation into CMOS compatible multimodule architectures to miniaturise the standard TCSPC set up, allow an increase in photon throughput by overcoming the TCSPC pile-up limit, and provide fluorescence lifetime calculations in real-time is presented. The investigation verifies the operation of the architectures and leads to the selection of optimal parameters for the number of detectors and timing channels required to overcome the TCSPC pile-up limit by at least an order of magnitude. The parameters are used to implement a low power miniaturised sensor in a 130 nm CMOS process, combining single photon detection, multiple channel timing and embedded pre-processing of the fluorescence lifetime, all within a silicon area of < 2 mm2. Single photon detection is achieved using an array of single photon avalanche diodes (SPADs) arranged in a digital silicon photomultiplier (SiPM) architecture with a 10 % fill-factor and a compressed 250 ps output pulse, which provides a photon throughput of > 700 MHz. An array of time-interleaved time-to-digital converters (TI-TDCs) with 50 ps resolution and no processing dead-time records up to eight photon events during each excitation period, significantly reducing the effect of TCSPC pile-up. The TCSPC data is then processed using an embedded centre-of-mass method (CMM) pre-calculation to produce single exponential fluorescence lifetime estimations in real-time. The combination of high photon throughput and real-time calculation enables advances in applications such as fluorescence lifetime imaging microscopy (FLIM) and time domain fluorescence lifetime activated cell sorting. To demonstrate this, the device is validated in practical bulk sample fluorescence lifetime, FLIM and simulated flow based experiments. Photon throughputs in excess of the excitation frequency are demonstrated for a range of organic and inorganic fluorophores for minimal error in lifetime calculation by CMM (< 5 %)

Adaptive Multimodule Routers

. Recent multiprocessors such as Cray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and switching hardware is partitioned into multiple modules, with each module suitable for implementation as a chip. This paper proposes a method to incorporate adaptivity into such routers with simple changes to the router structure and logic. We show that with as few as two virtual channels per physical channel, adaptivity can be provided to handle nonuniform traffic in multidimensional meshes. Keywords: adaptive routing, mesh networks, multicomputers, multimodule routers, wormhole routing. 1 Introduction Many recent experimental and commercial multicomputers and multiprocessors [6, 14, 18] use grid topology based networks such as meshes and tori. Majority of these multicomputers use the dimension-order or e-cube routing with wormhole (WH) switching [8]. Wormhole is a form of cutthrough routing in which blocked ..