SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation

Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a “VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques” framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole based DCT bases, and error can be analyzed through Parseval’s theorem. Practical examples are given to show the applicability of our proposed framework

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology

Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep Sub-Micron design. Post silicon bug due to noise and signal integrity can be prevented and fixed at early stage of the IC design cycle. The purpose of this research is to establish a preventive measurement for adjacent wire that can travel in parallel for 45nm technology. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and provide sign-off solution. Main approach is to conduct the relationship study between delta delay and adjacent parallel wire in 45 nanometer (nm) process technology and provide a preventive measurement to limit the adjacent wire can travel in parallel. The design is explored thoroughly to study the relationship between delay noise and adjacent parallel wire. The correlation is translated into an equation to estimate the delay noise produced with a certain length of adjacent parallel wire

EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS

Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description. At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance. For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs

System level power integrity transient analysis using a physics-based approach

With decreasing supply voltage level and massive demanding current on system chipset, power integrity design becomes more and more critical for system stability. The ultimate goal of well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise delivered to digital devices. The thesis is composed of three parts. The first part focuses on-die level power models including simplified chip power model (CPM) for system level analysis and the worst scenario current profile. The second part of this work introduces the physics-based equivalent circuit model to simplify the passive PDN model to RLC circuit netlist, to be compatible with any spice simulators and tremendously boost simulation speed. Then a novel system/chip level end-to-end transient model is proposed, including the die model and passive PDN model discussed in previous two chapters as well as a SIMPLIS based small signal VRM model. In the last part of the thesis, how to model voltage regulator module (VRM) is explicitly discussed. Different linear approximated VRM modeling approaches have been compared with the SIMPLIS small signal VRM model in both frequency domain and time domain. The comparison provides PI engineers a guideline to choose specific VRM model under specific circumstances. Finally yet importantly, a PDN optimization example was given. Other than previous PDN optimization approaches, a novel hybrid target impedance concept was proposed in this thesis, in order to improve system level PDN optimization process --Abstract, page iv

Improved attenuation and crosstalk modeling techniques for high-speed channels

”As digital systems are moving in the direction of faster data transmission rate and higher density of circuits, the problem of the far-end crosstalk (FEXT) and frequency-dependent attenuation are becoming the major factors that limit signal integrity performance. This research is focusing on providing several more comprehensive and accurate modeling approaches for striplines on fabricated printed circuit board (PCB). By characterizing the dielectric permittivity of prepreg and core, dielectric loss tangent, and copper foil surface roughness using measurement data, a better agreement between the stripline model and measurement is achieved. First, a method is proposed to extract dielectric loss tangent using coupled striplines’ measured S-parameters and cross-section geometry. By relating modal attenuation factors to the ratio between the differential and common mode per-unit-length resistances, the unknwon surface roughness contribution is eliminated and the contributions of dielectric and conductor loss are separated. In addition, an improved surface roughness modeling approach is proposed by analyzing the microscopical cross-sectional image of the stripline. By combining the characterized surface roughness information and the extracted dielectric properties, the modeled attenuation factor is match with the measurement data. At last, an approach is introduced to extract the dielectric permittivity of prepreg and core. Using known cross-sectional geometry and measured phase of the coupled stirplines under test, the capacitance components in prepreg and core are separated using 2D solver models. Using the stripline model with inhomogeneous dielectric material, more accurate FEXT modeling results are obtained”--Abstract, page iv

Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

The analysis and modeling of fine pitch laminate interconnect in response to large energy fault transients

In embedded applications, the miniaturization of circuitry and functionality provides many benefits to both the producer and consumer. However, the benefits gained from miniaturization is not without penalty, as the environmental influences may be great enough to introduce system failures in new or different modes and effects;Of particular interest within this research is the effect of fault transients in reduced geometries of printed circuit card interconnect, commonly referred to as fine pitch laminate interconnect. Whereas larger geometries of conductor trace width and spacing may have been immune to circuit failure at a given fault input, the reduction of the trace geometry may introduce failures as the insulating effect of the dielectric is compromised to the point where arcing occurs;To address this concern, a circuit card was designed with fine pitch laminate features in microstrip, embedded microstrip, and stripline constructions. Various trace widths and separations were tested for structural integrity (presence of arcing or fusing) at voltage extremes defined in avionics standard. The specific trace widths in the test were 4 mils, 6 mils, 8 mils, and 12 mils, with the trace separation in each case equal to the trace widths. The results of the tests and methods to artificially improve the integrity of the interconnect are documented, providing a clear region of reliable operation to the designers and the engineering community;Finally, the construction of the interconnect and the results from the test were combined to create an empirical model for circuit analysis. Created for the Saber simulator, but readily adaptable to Spice, this model will describe high-speed operation of a propagating signal before breakdown, and uses data from the experiment to calculate threshold values for the arcing breakdown. The values for the breakdown voltages are correlated to the experimental data using statistical methods of weighted linear regression and hypothesis testing