Accurate and Efficient Layout-to-Circuit Extraction for High-Speed MOS and Bipolar/BiCMOS Integrated Circuits

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by various simulation packages, such as Spice. The efficiency and accuracy of the extractor are confirmed by experimental results and enable a fast and reliable layout verification for both MOS and bipolar/BiCMOS technologies. 1 Introduction Today, layout verification for VLSI is a crucial part of IC design. For applicability, however, it must not only be fast and accurate, but it must also allow for various technologies. The layout-to-circuit extractor Space meets these constraints. It quickly translates a layout into an equivalent network that is an accurate model of that layout. Subsequently, circu..