Accurate VHDL-based simulation of Sigma Delta modulators

The computational cost of transient simulation of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) at the electrical level is prohibitively high. Behavioral simulation techniques offer a promising solution to this problem. This paper demonstrates that both hardware description languages (HDLs) and commercial HDL simulators constitute a valuable alternative to traditional special-purpose /spl Sigma//spl Delta/ behavioral simulators. In this sense, a library of HDL building blocks, modeling a complete set of circuit non-idealities which influence the performance of /spl Sigma//spl Delta/Ms, is presented. With these blocks, /spl Sigma//spl Delta/M architectures can be described in two different ways, which are analyzed in detail. Experimental results are provided through several simulations of a fourth-order 2-1-1 cascade multi-bit /spl Sigma//spl Delta/M