Accelerated Compact Test Set Generation for Three-State Circuits

Most published ATPG methods cannot handle threestate primitives, generate too large test sets, or require excessive CPU time. An efficient ATPG system was introduced in [1][2], which can handle non-Boolean primitives, generates compact test sets, within affordable CPU time. In this paper, the system is extended to handle pulled and wired buses, in addition to pure three-state buses. These bus types are widely used in industrial circuits. Furthermore five techniques for test generation are proposed to accelerate (compact) ATPG. Experimental results demonstrate that these new techniques are useful: ATPG times for compact test set generation are decreased up to 50% compared to [1], and fault efficiencies above 99% can be obtained for even the largest circuits. Keywords: ATPG, industrial circuits, compact test sets, three-state elements, wired buses, pulled buses. 1 Introduction Many efficient test pattern generation methods for combinational and full-scan synchronous circuits have been p..