ASIC Manufacturing Test Cost Prediction at Early Design Stage

This paper proposes a test cost prediction model which estimates the cost of IC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost. 1. INTRODUCTION VLSI technology has been enjoying a rapid growth of integration, which results in millions of components integrated on a single silicon die. Among VLSI chips, ASIC (Application Specific Integrated Circuit) chips have become more popular than others due to their application specific and high performance nature. However, the ever-increasing scale of integration causes many difficult problems in the testing of highly integrated ASICs. Increasing chip's complexity without employing correct DFT techniques usually results in increasing defect. Furthermore, the lack of methodology to predict the te..

Methodology and Ecosystem for the Design of a Complex Network ASIC

Performance of HPC systems has risen steadily. While the 10 Petaflop/s barrier has been breached in the year 2011 the next large step into the exascale era is expected sometime between the years 2018 and 2020. The EXTOLL project will be an integral part in this venture. Originally designed as a research project on FPGA basis it will make the transition to an ASIC to improve its already excelling performance even further. This transition poses many challenges that will be presented in this thesis. Nowadays, it is not enough to look only at single components in a system. EXTOLL is part of complex ecosystem which must be optimized overall since everything is tightly interwoven and disregarding some aspects can cause the whole system either to work with limited performance or even to fail. This thesis examines four different aspects in the design hierarchy and proposes efficient solutions or improvements for each of them. At first it takes a look at the design implementation and the differences between FPGA and ASIC design. It introduces a methodology to equip all on-chip memory with ECC logic automatically without the user’s input and in a transparent way so that the underlying code that uses the memory does not have to be changed. In the next step the floorplanning process is analyzed and an iterative solution is worked out based on physical and logical constraints of the EXTOLL design. Besides, a work flow for collaborative design is presented that allows multiple users to work on the design concurrently. The third part concentrates on the high-speed signal path from the chip to the connector and how it is affected by technological limitations. All constraints are analyzed and a package layout for the EXTOLL chip is proposed that is seen as the optimal solution. The last part develops a cost model for wafer and package level test and raises technological concerns that will affect the testing methodology. In order to run testing internally it proposes the development of a stand-alone test platform that is able to test packaged EXTOLL chips in every aspect