A 0.18 µm differential LNA with reduced power consumption

The growth of wireless services and other telecom applications has increased the demand of low-cost Radio-Frequency Integrated Circuits (RFICs) and pushed the semiconductor industry towards complete system-on-chip solutions. This work presents the design of an inductively source degenerated CMOS differential cascode Low Noise Amplifier (LNA) and without source degenerated CMOS differential cascode Low Noise Amplifier (LNA) operating at 2 GHz frequency. LNA is an electronic device used to amplify weak signals before it can be fed to other parts of the receiver. A good LNA has a low noise figure (NF), a large enough gain and low power consumption. During reception of radio signal sent by satellite in a communication system, in the receiver section, second element after antenna is LNA. The receiver is the most power hungry block and the power consumption should be as low as possible. So, noise figure and power consumption are no less important issues than gain. A Differential Cascode Low Noise Amplifier can be treated as a CS-CG two stage amplifier. An inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. Another inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and to increase power gain of the cascode transistors in a Differential Cascode LNA. It can reduce the power consumption, and increase the power gain of the LNA. The area occupied by the proposed design measured from the layout is observed as 1.111 mm × 1.27 mm. The LNA is designed with the 0.18 µm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors