Modeling of Hardware and Software for specifying Hardware Abstraction Layers

International audienceIn this paper we describe a practical approach for modeling low level interfaces between software and hardware parts based on SysML operations. This method is intended to be applied for the development of drivers involved on what is classically called the “hardware abstraction layer” or the “basic software” which provide high level services for resources management on the top of a bare hardware platform. It is also an enabler for co-design processes since the design of hardware and software can be decoupled. In addition this approach is compatible with virtual prototyping technologies such as SystemC/TLM. An application to a simple a study case is provided for illustration purpose

A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design

ISBN:1-59593-091-4One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a discontinuity between hardware and software. This paper introduces a unified HW/SW component model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow

Méthodes de raffinement des communications pour passer d'une plate-forme systemc à un système reprogrammable

Revue du raffinement des communications pour systèmes sur puce -- Le modèle TLM -- Les systèmes sur puce -- Modèles de communication pour un SoC -- Éléments du raffinement de SoC -- Revue des travaux sur le raffinement -- La plateforme Space -- La librairie SystemC -- Raffinement des communications de Space -- Les outils de développement -- Méthodologie -- Implémentation au niveau RTL -- Comparaison avec les autres travaux de recherche -- Résultats, discussions et améliorations -- Quelques restrictions de fonctionnmeent de l'IPIF -- Latences des communications matériel-matériel -- Latence des communications entre le matériel et le logiciel -- La profondeur des FIFO d'envoi et de réception -- Utilisation des ressources et fréquence maximale