A Traffic-Balanced Routing Scheme for Heat Balance in 3D Networks-on-Chip

Network-on-Chip (NoC) is designed to tackle the architectural scalability and interconnection problems in many-core architectures. Multiple layers are stacked together using through silicon vias (TSV) and establish inter-die connectivity in the 3D integration technology. In 3D NoC, the congestion problem and the thermal problem are the major issues. Once the congestion problem occurs, the performance of 3D NoC rapidly degrades such as increasing transmission latency, extra power consumption, higher temperature and imbalanced traffic among different logic layers. In addition, the effect of high temperature also increases transmission latency, leakage power, and cooling cost. In this thesis, an advanced temporary relay routing (ATRR) algorithm is proposed to achieve three goals: (1) collecting the information of congestion and throttling to balance traffic; (2) reducing path diversities (PD) to improve the average latency; (3) adjusting routing paths to dissipate heat in 3D NoC. Simulation results validated by mathematical analysis show that the proposed scheme can improve average latency, approach better heat balance, as well as obtain high scalability.晶片網路被設計來克服多核心系統的架構擴充性和互聯問題。在3D整合技術中，多層晶片利用矽穿孔(through silicon vias，TSV)垂直堆疊互聯。 擁塞問題和熱的問題是3D晶片網路的主要議題。只要擁塞一發生，3D晶片網路的效能隨之降級，進而增加傳輸延遲，額外能量消耗，過高的溫度產生以及各晶片層間不平衡的流量。除此，高溫度的產生導致延遲提高，漏電流的功耗增加，冷卻晶片的成本升高。 因此，本論文提出一個高級暫時性中繼節點路由(advanced temporary relay routing, ATRR)演算法策略，該演算法達成了三項目標: (1)收集網路上擁塞和節流的資訊去平衡流量(2)減少路徑的發散性去改善系統平均延遲(3)調整路由路徑去減少3D晶片網路的熱。 實驗模擬結果透過數學分析驗證，本論文提出的策略不僅改善系統的平均延遲，使系統更趨於熱平衡，也得到更高的擴充性。Acknowledgements i 摘要 ii Abstract iii Table of Contents iv List of Figures vi Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Motivation and Distribution 2 1.3 The Architecture of This Thesis 3 Chapter 2 Background Knowledge 4 2.1 Run-time Thermal Management of 3D NoC 4 2.2 Conventional Congestion Schemes 5 2.3 Selection Function Schemes 5 Chapter 3 Advanced Temporary Relay Routing Algorithm 7 3.1 The Concept of ATRR 7 3.2 Congestion and Throttling Information Table (CTIT) 10 3.3 Temporary Relay Mechanism (TR) 12 3.4 Adaptive Buffer Level Selection (ABL) 19 Chapter 4 Analytical Model of ATRR 22 4.1 Basic Assumptions and Notation 22 4.2 Analytical Delay Model of TR 29 4.3 Analytical Delay Model of ABL 34 4.4 Analytical Results 36 4.4 .1 The Verification of TR 37 4.4 .3 The Verification of Analytical Model 41 Chapter 5 Experiment Results 42 5.1 Simulation Environment 42 5.2 The Performance of ATRR Scheme 44 5.3 The Scalability of ATRR 48 5.4 The Effect of Different Number in ATRR 51 5.5 The Verification of ABL 55 Chapter 6 Conclusions 57 References 5