Abstract—We prove a theorem stating that the test time of digital test is obtained upon dividing the total energy dissipated during test by the average rate of consumption or power. As we try to reduce the test time, the critical path delay (structural constraint) and the peak power capability of the circuit (power constraint) limit our capability to increase the rate of energy consumption. The theorem leads to two modes of testing, namely, synchronous and asynchronous. Supply voltage plays a significant role in optimizing the test time. I