A Survey on Compiler Autotuning using Machine Learning

Since the mid-1990s, researchers have been trying to use machine-learning based approaches to solve a number of different compiler optimization problems. These techniques primarily enhance the quality of the obtained results and, more importantly, make it feasible to tackle two main compiler optimization problems: optimization selection (choosing which optimizations to apply) and phase-ordering (choosing the order of applying optimizations). The compiler optimization space continues to grow due to the advancement of applications, increasing number of compiler optimizations, and new target architectures. Generic optimization passes in compilers cannot fully leverage newly introduced optimizations and, therefore, cannot keep up with the pace of increasing options. This survey summarizes and classifies the recent advances in using machine learning for the compiler optimization field, particularly on the two major problems of (1) selecting the best optimizations and (2) the phase-ordering of optimizations. The survey highlights the approaches taken so far, the obtained results, the fine-grain classification among different approaches and finally, the influential papers of the field.Comment: version 5.0 (updated on September 2018)- Preprint Version For our Accepted Journal @ ACM CSUR 2018 (42 pages) - This survey will be updated quarterly here (Send me your new published papers to be added in the subsequent version) History: Received November 2016; Revised August 2017; Revised February 2018; Accepted March 2018

Automated Bus Generation for Multi-processor SoC Design

In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.Ph.D.Committee Chair: Mooney, Vincent J.; Committee Member: Benkeser, Paul J.; Committee Member: Davis, Jeffrey A.; Committee Member: Starner, Thad; Committee Member: Yalamanchili, Sudhaka

Orthogonal-Array based Design Methodology for Complex, Coupled Space Systems

The process of designing a complex system, formed by many elements and sub-elements interacting between each other, is usually completed at a system level and in the preliminary phases in two major steps: design-space exploration and optimization. In a classical approach, especially in a company environment, the two steps are usually performed together, by experts of the field inferring on major phenomena, making assumptions and doing some trial-and-error runs on the available mathematical models. To support designers and decision makers during the design phases of this kind of complex systems, and to enable early discovery of emergent behaviours arising from interactions between the various elements being designed, the authors implemented a parametric methodology for the design-space exploration and optimization. The parametric technique is based on the utilization of a particular type of matrix design of experiments, the orthogonal arrays. Through successive design iterations with orthogonal arrays, the optimal solution is reached with a reduced effort if compared to more computationally-intense techniques, providing sensitivity and robustness information. The paper describes the design methodology in detail providing an application example that is the design of a human mission to support a lunar base

Optimisation of Mobile Communication Networks - OMCO NET

The mini conference “Optimisation of Mobile Communication Networks” focuses on advanced methods for search and optimisation applied to wireless communication networks. It is sponsored by Research & Enterprise Fund Southampton Solent University. The conference strives to widen knowledge on advanced search methods capable of optimisation of wireless communications networks. The aim is to provide a forum for exchange of recent knowledge, new ideas and trends in this progressive and challenging area. The conference will popularise new successful approaches on resolving hard tasks such as minimisation of transmit power, cooperative and optimal routing

A robust design methodology suitable for application to one-off products

Robust design is an activity of fundamental importance when designing large, complex, one-off engineering products. Work is described which is concerned with the application of the theory of design of experiments and stochastic optimization methods to explore and optimize at the concept design stage. The discussion begins with a description of state-of-the-art stochastic techniques and their application to robust design. The content then focuses on a generic methodology which is capable of manipulating design algorithms that can be used to describe a design concept. An example is presented, demonstrating the use of the system for the robust design of a catamaran with respect to seakeeping