6,800 research outputs found
A Survey of Techniques for Improving Security of GPUs
Graphics processing unit (GPU), although a powerful performance-booster, also
has many security vulnerabilities. Due to these, the GPU can act as a
safe-haven for stealthy malware and the weakest `link' in the security `chain'.
In this paper, we present a survey of techniques for analyzing and improving
GPU security. We classify the works on key attributes to highlight their
similarities and differences. More than informing users and researchers about
GPU security techniques, this survey aims to increase their awareness about GPU
security vulnerabilities and potential countermeasures
Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File
Modern graphics processing units (GPUs) are
using increasingly larger register file (RF) which occupies
a
large fraction of GPU core area and is very frequently access
ed.
This makes RF vulnerable to soft-errors (SE). In this paper,
we
present two techniques for improving SE resilience of GPU RF
.
First, we propose compressing the RF values for reducing the
number of vulnerable bits. We leverage value similarity and
the presence of narrow-width values to perform compression
at
warp or thread-level, respectively. Second, we propose sel
ective
hardening to design a portion of register entry with SE immun
e
circuits. By collectively using these techniques, higher r
esilience
can be provided with lower overhead. Without hardening, our
warp and thread-level compression techniques bring 47.0%
and 40.8% reduction in SE vulnerability, respectively
A Survey of Techniques for Architecting TLBs
“Translation lookaside buffer” (TLB) caches virtual to physical address translation information and is used
in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently
and a TLB miss is extremely costly, prudent management of TLB is important for improving performance
and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and
managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and
distinctions. We believe that this paper will be useful for chip designers, computer architects and system
engineers
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