IEEE 2009 Custom Intergrated Circuits Conference (CICC) A Sub-0.75°RMS-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique

Abstract—This paper presents a low-phase-error wideband fractional-N frequency synthesizer. Differential tuning is described and a level shift circuit is proposed to obtain symmetrical tuning range. On-chip LDO regulator is designed to improve the power supply rejection for VCO. A voltage monitor is used to enhance the digital AFC technique to overcome the temperature variation. The synthesizer was implemented in a 0.18-μm CMOS process with a 16-mA supply current and a 1.47-mm 2 die area. The measured in-band phase noise is less than –97 dBc/Hz at a 10-kHz frequency offset and the integrated phase error is less than 0.75°RMS. The measured reference spur is less than –71 dBc and the locking time is smaller than 20 μs. I