Efficient Low Power Headphone Driver

In recent years, the consumer electronics market for battery-powered devices such as smartphones and tablets has been rapidly expanding. The requirements for audio CODEC in these portable devices have extended from merely supporting voice calls to high-fidelity music playback. As a result, audio driver performance has become one of the most important differentiating factors among products from different suppliers. There are three basic performance metrics that are typically used to benchmark audio modules: the maximum delivered output power, the audio fidelity measured in terms of dynamic range, THD+N, and finally the battery life. Maximizing all three of these performance metrics has proven to be an exceptionally hard task as portrayed by the research publications.This work presents an attempt to push all three of these metrics together and provide an acceptable balance which is achieved by selecting the right topology. Conventionally, headphone drivers are designed using a linear amplifier topology for many reasons- most prominently- to achieve a superior THD+N and PSRR requirement which in the past was essentially the only key performance metric needed. This came at the expense of realizing mediocre power efficiency targets, thereby wasting battery life. This picture changed dramatically over the last decade with smartphones and other portable devices becoming the first choice of the young generation. These devices are extremely power hungry due to the unlimited functions and features they provide and therefore battery life has come to the spotlight as a key resource that need to be preserved. As a result, in this work a headphone driver is based on a switching topology that is able to deliver more than 230mW of power (or equivalently 2Vrms) to a 16Ω load while achieving better than -98dB of THD+N , more than 108dB of SNR, and about 108dB PSRR while still maintaining a peak power efficiency of more than 84%

Low-voltage data converters

With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve the reliability of gate dielectrics. While the reduction of power supply voltage is of great benefit to the essential digital blocks in the system like data storage and digital signal processing, it makes it hard to operate the important and indispensable analog building blocks such as data converters and drivers. In this thesis, the novel structures for the low-voltage digital-to-analog converter (DAC) and analog-to-digital converter (ADC) are presented. The research contributions of this work include (1) a sub-1V audio [delta sigma] DAC with one opamp used per channel to implement D/A conversion, 1st-order FIR and 2ndorder IIR filtering, as well as power amplification for the headphone, (2) a sub-1V pipelined ADC with the novel MDAC based on a low-voltage track-and-hold amplifier. Two prototypes, one is a 0.8V, 88dB dual-channel audio [delta sigma] DAC with headphone driver, the other one is a 0.8V, 10-bit, 10MS/s pipelined ADC were fabricated to verify the functionality of the proposed structures in standard CMOS processes

Study and design of an interface for remote audio processing

This project focused on the study and design of an interface for remote audio processing, with the objective of acquiring by filtering, biasing, and amplifying an analog signal before digitizing it by means of two MCP3208 ADCs to achieve a 24-bit resolution signal. The resulting digital signal was then transmitted to a Raspberry Pi using SPI protocol, where it was processed by a Flask server that could be accessed from both local and remote networks. The design of the PCB was a critical component of the project, as it had to accommodate various components and ensure accurate signal acquisition and transmission. The PCB design was created using KiCad software, which allowed for the precise placement and routing of all components. A major challenge in the design of the interface was to ensure that the analog signal was not distorted during acquisition and amplification. This was achieved through careful selection of amplifier components and using high-pass and low-pass filters to remove any unwanted noise. Once the analog signal was acquired and digitized, the resulting digital signal was transmitted to the Raspberry Pi using SPI protocol. The Raspberry Pi acted as the host for a Flask server, which could be accessed from local and remote networks using a web browser. The Flask server allowed for the processing of the digital signal and provided a user interface for controlling the gain and filtering parameters of the analog signal. This enabled the user to adjust the signal parameters to suit their specific requirements, making the interface highly flexible and adaptable to a variety of audio processing applications. The final interface was capable of remote audio processing, making it highly useful in scenarios where the audio signal needed to be acquired and processed in a location separate from the user. For example, it could be used in a recording studio, where the audio signal from the microphone could be remotely processed using the interface. The gain and filtering parameters could be adjusted in real-time, allowing the sound engineer to fine-tune the audio signal to produce the desired recording. In conclusion, the project demonstrated the feasibility and potential benefits of using a remote audio processing system for various applications. The design of the PCB, selection of components, and use of the Flask server enabled the creation of an interface that was highly flexible, accurate, and adaptable to a variety of audio processing requirements. Overall, the project represents a significant step forward in the field of remote audio processing, with the potential to benefit many different applications in the future

High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio

Recent advances in the hardware architecture of flat display devices

Thesis (Master)--Izmir Institute of Technology, Electronics and Communication Engineering, Izmir, 2007Includes bibliographical References (leaves: 115-117)Text in English; Abstract: Turkish and Englishxiii, 133 leavesThesis will describe processing board hardware design for flat panel displays with integrated digital reception, the design challenges in flat panel displays with integrated digital reception explained with details. Thesis also includes brief explanation of flat panel technology and processing blocks. Explanations of building blocks of TV and flat panel displays are given before design stage for better understanding of design stage. Hardware design stage of processing board is investigated in two major steps, schematic design and layout design. First step of the schematic design is system level block diagram design. Schematic diagram is the detailed application level hardware design and layout is the implementation level of the design. System level, application level and implementation level hardware design of the TV processing board is described with details in thesis. Design challenges, considerations and solutions are defined in advance for flat panel displays

Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling

Real-time digital signal processing system for normal probe diffraction technique

Ultrasonic systems are widely used in many fields of non-destructive testing. The increasing requirement for high quality steel product stirs the improvement of both ultrasonic instruments and testing methods. The thesis indicates the basics of ultrasonic testing and Digital Signal Processing (DSP) technology for the development of an ultrasonic system. The aim of this project was to apply a new ultrasonic testing method - the Normal Probe Diffraction method to course grained steel in real-time and investigate whether the potential of probability of detection (POD) has been improved. The theories and corresponding experiment set-up of pulse-echo method, TOFD and NPD method are explained and demonstrated separately. A comparison of these methods shows different contributions made by these methods using different types of algorithms and signals. Non-real-time experiments were carried out on a VI calibration block using an USPC 3100 ultrasonic testing card to implement pulse-echo and NPD method respectively. The experiments and algorithm were simulated and demonstrated in Matlab. A low frequency Single-transmitter-multi-receiver ultrasonic system was designed and built with a digital development board and an analogue daughter card to transmit or receive signals asynchronously. A high frequency high voltage amplifier was designed to drive the ultrasonic probes. A Matlab simulation system built with Simulink indicates that the Signal to Noise Ratio (SNR) can be improved with an increment of up to 3dB theoretically based on the simulation results using DSP techniques. The DSP system hardware and software was investigated and a real-time DSP hardware system was supposed to be built to implement the high frequency system using a rapid code generated system based on Matlab Simulink model and the method was presented. However, extra effort needs to be taken to program the hardware using a low-level computer language to make the system work stably and efficiently

Low Power High Efficiency Integrated Class-D Amplifier Circuits for Mobile Devices

The consumer’s demand for state-of-the-art multimedia devices such as smart phones and tablet computers has forced manufacturers to provide more system features to compete for a larger portion of the market share. The added features increase the power consumption and heat dissipation of integrated circuits, depleting the battery charge faster. Therefore, low-power high-efficiency circuits, such as the class-D audio amplifier, are needed to reduce heat dissipation and extend battery life in mobile devices. This dissertation focuses on new design techniques to create high performance class-D audio amplifiers that have low power consumption and occupy less space. The first part of this dissertation introduces the research motivation and fundamentals of audio amplification. The loudspeaker’s operation and main audio performance metrics are examined to explain the limitations in the amplification process. Moreover, the operating principle and design procedure of the main class-D amplifier architectures are reviewed to provide the performance tradeoffs involved. The second part of this dissertation presents two new circuit designs to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers. The first work proposes a feed-forward power-supply noise cancellation technique for single-ended class-D amplifier architectures to improve the power-supply rejection ratio across the entire audio frequency range. The design methodology, implementation, and tradeoffs of the proposed technique are clearly delineated to demonstrate its simplicity and effectiveness. The second work introduces a new class-D output stage design for piezoelectric speakers. The proposed design uses stacked-cascode thick-oxide CMOS transistors at the output stage that makes possible to handle high voltages in a low voltage standard CMOS technology. The design tradeoffs in efficiency, linearity, and electromagnetic interference are discussed. Finally, the open problems in audio amplification for mobile devices are discussed to delineate the possible future work to improve the performance of class-D amplifiers. For all the presented works, proof-of-concept prototypes are fabricated, and the measured results are used to verify the correct operation of the proposed solutions