Design of Reversible Quantum Logic Structures in CMOS Technology

Reversible logic gates have an equal number of inputs and outputs, which also makes it possible to reverse calculate and reconstruct the inputs from the outputs. Quantum logic elements are inherently reversible and requires very little energy to operate. Some of the most common uses of Quantum Computers are in the design of Convolutional Neural Networks (CNN), Deep Neural Networks (DNN) and for machine learning (ML) purposes. In this research, the reversible logic gates were designed with 45ηm CMOS technology modeled after reversible quantum logic gates. As a proof of concept, hardware that provided Sigmoid Neuron Functionality was carried out by processing the MNIST Dataset, a handwritten digit database for number recognition

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

The reversible logic function is gaining significant consideration as a style for the logic design by implementing modern Nano and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow for computer design applications using advanced quantum computer algorithms. In the literature, significant contributions have been made towards reversible logic gate structures and arithmetic units. However, there are many attempts to dictate the design of Single Instruction-Multiple Data (SIMD) processors. In this research work, a novel programmable reversible logic gate design is verified and a reversible processor design suggests its implementation of SIMD processor. Then, implementing the ripple-carry, carry-select and Kogge-Stone carry look-ahead adders using reversible logic and the performance is compared. The proposed reversible logic-based architecture has a minimum fan out with binary tree structure and minimum logic depth. The simulation result of the proposed design is obtained from Xilinx 14.5 software. From the simulated result, the computational path net delay for 16 × 16 reversible logic with Kogge Stone Adder is 17.247 ns. Compared with 16-bit Kogge Stone Adder, the reversible logic-based 16-bit Kogge Stone Adder gives low power and low time delay. By looking at the speed, energy and area parameters, including fast applications in which two smaller delay and low power adders are required, the effectiveness, including the proper area use of the hybrid adder recommended by it is evaluated

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

In this paper, the authors propose the idea of a combined integer and floating point multiplier(CIFM) for FPGAs. The authors propose the replacement of existing 18x18 dedicated multipliers in FPGAs with dedicated 24x24 multipliers designed with small 4x4 bit multipliers. It is also proposed that for every dedicated 24x24 bit multiplier block designed with 4x4 bit multipliers, four redundant 4x4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24x24 bit multiplier stems from the fact that single precision floating point multiplier requires 24x24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4x4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.Comment: Published in the proceedings of the The 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August 2006. Nominated for the Student Paper Award(12 papers are nominated for Student paper Award among all submissions