A PROGRAMMABLE ACCELERATOR FOR NEXT GENERATION WIRELESS COMMUNICATIONS

We present a MIMO decoder accelerator architecture that offers versatility and re-programmability while maintaining a very high performance-cost metric. The accelerator is meant to address the MIMO decoding bottlenecks associated with the convergence of multiple high speed wireless standards onto a single device. It is scalable in the number of antennas, bandwidth, modulation format, and most importantly, present and emerging decoder algorithms. It features a Harvard-like architecture with complex vector operands and a deeply pipelined fixed-point complex arithmetic processing unit. Memory allows efficient access to operands in matrix form, while a custom state machine enhances performance in light of OFDM. The accelerator shows an advantage of up to 3 orders of magnitude in power-delay product for typical MIMO decoding operations relative to a general purpose DSP. 1