A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits

This paper presents a practical approach to parasitic extraction enabling accurate timing and crosstalk analyses throughout the design cycle. New error indexes are first proposed for evaluating the accuracy of flat parasitic extraction. The requirements for extraction in hierarchical design flows are then discussed. The methodology reported aims at reducing the gap between the parasitic values estimated with incomplete design and the results of post-layout extraction. The objective is to obtain consistent interconnect models in top-down and bottom-up design flows. This methodology was integrated into the design flow for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses