A Performance Driven Generator for Efficient Testable Conditional-Sum-Adders (Extended Abstract)

We present a performance driven generator for integer adders which is parametrized in n, the operands' bit length, tn , the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area minimal n-bit adder of the conditional-sum type with delay tn (if such a circuit exists, at all) and a test set which is complete w.r.t. the chosen fault model FM . The number of test vectors constructed is bounded by O(n 2 ). The running time of the generator itself is about c\Deltan 2 \Deltat n where c is a small constant