Reduced Complexity Sphere Decoding

In Multiple-Input Multiple-Output (MIMO) systems, Sphere Decoding (SD) can achieve performance equivalent to full search Maximum Likelihood (ML) decoding, with reduced complexity. Several researchers reported techniques that reduce the complexity of SD further. In this paper, a new technique is introduced which decreases the computational complexity of SD substantially, without sacrificing performance. The reduction is accomplished by deconstructing the decoding metric to decrease the number of computations and exploiting the structure of a lattice representation. Furthermore, an application of SD, employing a proposed smart implementation with very low computational complexity is introduced. This application calculates the soft bit metrics of a bit-interleaved convolutional-coded MIMO system in an efficient manner. Based on the reduced complexity SD, the proposed smart implementation employs the initial radius acquired by Zero-Forcing Decision Feedback Equalization (ZF-DFE) which ensures no empty spheres. Other than that, a technique of a particular data structure is also incorporated to efficiently reduce the number of executions carried out by SD. Simulation results show that these approaches achieve substantial gains in terms of the computational complexity for both uncoded and coded MIMO systems.Comment: accepted to Journal. arXiv admin note: substantial text overlap with arXiv:1009.351

Channel coded iterative center-shifting K-best sphere detection for rank-deficient systems

Based on an EXtrinsic Information Transfer (EXIT) chart assisted receiver design, a low-complexity near-Maximum A Posteriori (MAP) detector is constructed for high-throughput MIMO systems. A high throughput is achieved by invoking high-order modulation schemes and/or multiple transmit antennas, while employing a novel sphere detector (SD) termed as a center-shifting SD scheme, which updates the SD’s search center during its consecutive iterations with the aid of channel decoder. Two low-complexity iterative center-shifting SD aided receiver architectures are investigated, namely the direct-hard-decision centershifting (DHDC) and the direct-soft-decision center-shifting (DSDC) schemes. Both of them are capable of attaining a considerable memory and complexity reduction over the conventional SD-aided iterative benchmark receiver. For example, the DSDC scheme reduces the candidate-list-generation-related and extrinsic-LLR-calculation related complexity by a factor of 3.5 and 16, respectively. As a further benefit, the associated memory requirements were also reduced by a factor of 16

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

A universal space-time architecture for multiple-antenna aided systems

In this tutorial, we first review the family of conventional multiple-antenna techniques, and then we provide a general overview of the recent concept of the powerful Multiple-Input Multiple-Output (MIMO) family based on a universal Space-Time Shift Keying (STSK) philosophy. When appropriately configured, the proposed STSK scheme has the potential of outperforming conventional MIMO arrangements

On the MIMO Channel Capacity of Multi-Dimensional Signal Sets

In this contribution we evaluate the capacity of Multi-Input Multi-Output (MIMO) systems using multi-dimensional PSK/QAM signal sets. It was shown that transmit diversity is capable of narrowing the gap between the capacity of the Rayleigh-fading channel and the AWGN channel. However, since this gap becomes narrower when the receiver diversity order is increased, for higher-order receiver diversity the performance advantage of transmit diversity diminishes. A MIMO system having full multiplexing gain has a higher achievable throughput than the corresponding MIMO system designed for full diversity gain, although this is attained at the cost of a higher complexity and a higher SNR. The tradeoffs between diversity gain, multiplexing gain, complexity and bandwidth are studied