13,793 research outputs found

    Shortest path routing algorithm for hierarchical interconnection network-on-chip

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    Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path

    On hardware for generating routes in Kautz digraphs

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    In this paper we present a hardware implementation of an algorithm for generating node disjoint routes in a Kautz network. Kautz networks are based on a family of digraphs described by W.H. Kautz[Kautz 68]. A Kautz network with in-degree and out-degree d has N = dk + dkÂż1 nodes (for any cardinals d, k>0). The diameter is at most k, the degree is fixed and independent of the network size. Moreover, it is fault-tolerant, the connectivity is d and the mapping of standard computation graphs such as a linear array, a ring and a tree on a Kautz network is straightforward.\ud The network has a simple routing mechanism, even when nodes or links are faulty. Imase et al. [Imase 86] showed the existence of d node disjoint paths between any pair of vertices. In Smit et al. [Smit 91] an algorithm is described that generates d node disjoint routes between two arbitrary nodes in the network. In this paper we present a simple and fast hardware implementation of this algorithm. It can be realized with standard components (Field Programmable Gate Arrays)

    A multipath analysis of biswapped networks.

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    Biswapped networks of the form Bsw(G)Bsw(G) have recently been proposed as interconnection networks to be implemented as optical transpose interconnection systems. We provide a systematic construction of Îș+1\kappa+1 vertex-disjoint paths joining any two distinct vertices in Bsw(G)Bsw(G), where Îș≄1\kappa\geq 1 is the connectivity of GG. In doing so, we obtain an upper bound of max⁥{2Δ(G)+5,ΔÎș(G)+Δ(G)+2}\max\{2\Delta(G)+5,\Delta_\kappa(G)+\Delta(G)+2\} on the (Îș+1)(\kappa+1)-diameter of Bsw(G)Bsw(G), where Δ(G)\Delta(G) is the diameter of GG and ΔÎș(G)\Delta_\kappa(G) the Îș\kappa-diameter. Suppose that we have a deterministic multipath source routing algorithm in an interconnection network GG that finds Îș\kappa mutually vertex-disjoint paths in GG joining any 22 distinct vertices and does this in time polynomial in ΔÎș(G)\Delta_\kappa(G), Δ(G)\Delta(G) and Îș\kappa (and independently of the number of vertices of GG). Our constructions yield an analogous deterministic multipath source routing algorithm in the interconnection network Bsw(G)Bsw(G) that finds Îș+1\kappa+1 mutually vertex-disjoint paths joining any 22 distinct vertices in Bsw(G)Bsw(G) so that these paths all have length bounded as above. Moreover, our algorithm has time complexity polynomial in ΔÎș(G)\Delta_\kappa(G), Δ(G)\Delta(G) and Îș\kappa. We also show that if GG is Hamiltonian then Bsw(G)Bsw(G) is Hamiltonian, and that if GG is a Cayley graph then Bsw(G)Bsw(G) is a Cayley graph

    A Switch Architecture for Real-Time Multimedia Communications

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    In this paper we present a switch that can be used to transfer multimedia type of trafJic. The switch provides a guaranteed throughput and a bounded latency. We focus on the design of a prototype Switching Element using the new technology opportunities being offered today. The architecture meets the multimedia requirements but still has a low complexity and needs a minimum amount of hardware. A main item of this paper will be the background of the architectural design decisions made. These include the interconnection topology, buffer organization, routing and scheduling. The implementation of the switching fabric with FPGAs, allows us to experiment with switching mode, routing strategy and scheduling policy in a multimedia environment. The witching elements are interconnected in a Kautz topology. Kautz graphs have interesting properties such as: a small diametec the degree is independent of the network size, the network is fault-tolerant and has a simple routing algorithm
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