A new class of very low sensitivity cascade-form digital-filters based on "passive" second order single-input single-output building blocks

A new type of cascade form structure for digital filtering is proposed, with each building block being a second order section, that satisfies certain passivity properties. This passivity is essentially a "structure-induced" boundedness on the transfer function magnitude, and leads to low passband sensitivity. In addition, the cascade nature ensures low stopband sensitivity, as zeros on the unit circle continue to remain on the unit circle in spite of the quantization. The structure itself is independent of the pole locations and therefore meets a wide range of filtering applications

Low passband sensitivity digital filters: A generalized viewpoint and synthesis procedures

The concepts of losslessness and maximum available power are basic to the low-sensitivity properties of doubly terminated lossless networks of the continuous-time domain. Based on similar concepts, we develop a new theory for low-sensitivity discrete-time filter structures. The mathematical setup for the development is the bounded-real property of transfer functions and matrices. Starting from this property, we derive procedures for the synthesis of any stable digital filter transfer function by means of a low-sensitivity structure. Most of the structures generated by this approach are interconnections of a basic building block called digital "two-pair," and each two-pair is characterized by a lossless bounded-real (LBR) transfer matrix. The theory and synthesis procedures also cover special cases such as wave digital filters, which are derived from continuous-time networks, and digital lattice structures, which are closely related to unit elements of distributed network theory

A new approach to the realization of low-sensitivity IIR digital filters

A new implementation of an IIR digital filter transfer function is presented that is structurally passive and, hence, has extremely low pass-band sensitivity. The structure is based on a simple parallel interconnection of two all-pass sections, with each section implemented in a structurally lossless manner. The structure shares a number of properties in common with wave lattice digital filters. Computer simulation results verifying the low-sensitivity feature are included, along with results on roundoff noise/dynamic range interaction. A large number of alternatives is available for the implementation of the all-pass sections, giving rise to the well-known wave lattice digital filters as a specific instance of the implementation

The role of lossless systems in modern digital signal processing: a tutorial

A self-contained discussion of discrete-time lossless systems and their properties and relevance in digital signal processing is presented. The basic concept of losslessness is introduced, and several algebraic properties of lossless systems are studied. An understanding of these properties is crucial in order to exploit the rich usefulness of lossless systems in digital signal processing. Since lossless systems typically have many input and output terminals, a brief review of multiinput multioutput systems is included. The most general form of a rational lossless transfer matrix is presented along with synthesis procedures for the FIR (finite impulse response) case. Some applications of lossless systems in signal processing are presented

Design of doubly-complementary IIR digital filters using a single complex allpass filter, with multirate applications

It is shown that a large class of real-coefficient doubly-complementary IIR transfer function pairs can be implemented by means of a single complex allpass filter. For a real input sequence, the real part of the output sequence corresponds to the output of one of the transfer functions G(z) (for example, lowpass), whereas the imaginary part of the output sequence corresponds to its "complementary" filter H(z)(for example, highpass). The resulting implementation is structurally lossless, and hence the implementations of G(z) and H(z) have very low passband sensitivity. Numerical design examples are included, and a typical numerical example shows that the new implementation with 4 bits per multiplier is considerably better than a direct form implementation with 9 bits per multiplier. Multirate filter bank applications (quadrature mirror filtering) are outlined

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Basics of RF electronics

RF electronics deals with the generation, acquisition and manipulation of high-frequency signals. In particle accelerators signals of this kind are abundant, especially in the RF and beam diagnostics systems. In modern machines the complexity of the electronics assemblies dedicated to RF manipulation, beam diagnostics, and feedbacks is continuously increasing, following the demands for improvement of accelerator performance. However, these systems, and in particular their front-ends and back-ends, still rely on well-established basic hardware components and techniques, while down-converted and acquired signals are digitally processed exploiting the rapidly growing computational capability offered by the available technology. This lecture reviews the operational principles of the basic building blocks used for the treatment of high-frequency signals. Devices such as mixers, phase and amplitude detectors, modulators, filters, switches, directional couplers, oscillators, amplifiers, attenuators, and others are described in terms of equivalent circuits, scattering matrices, transfer functions; typical performance of commercially available models is presented. Owing to the breadth of the subject, this review is necessarily synthetic and non-exhaustive. Readers interested in the architecture of complete systems making use of the described components and devoted to generation and manipulation of the signals driving RF power plants and cavities may refer to the CAS lectures on Low-Level RF.Comment: 36 pages, contribution to the CAS - CERN Accelerator School: Specialised Course on RF for Accelerators; 8 - 17 Jun 2010, Ebeltoft, Denmar

Interleavers

The chapter describes principles, analysis, design, properties, and implementations of optical frequency (or wavelength) interleavers. The emphasis is on finite impulse response devices based on cascaded Mach-Zehnder-type filter elements with carefully designed coupling ratios, the so-called resonant couplers. Another important class that is discussed is the infinite impulse response type, based on e.g. Fabry-Perot, Gires-Tournois, or ring resonators

Minimum power design of RF front ends

This thesis describes an investigation into the design of RF front ends with minimum power dissipation. The central question is: "What are the fundamental limits for the power dissipation of telecommunication front ends, and what design procedures can be followed that approach these limits and, at the same time, result in practical circuits?" After a discussion of the state of the art in this area, the elementary operations of a front end are identified. For each of these elementary operations, the fundamental limits for the power dissipation are discussed, divided into technology imposed limits and physics imposed limits. A traditional DECT front end design is used to demonstrate the large difference between the fundamental limits and the power dissipation of existing circuits. To improve this situation, first the optimum distribution of specifications across individual subcircuits needs to be determined, such that the requirements for a specific system can be fulfilled. This is achieved through the introduction of formal transforms of the specifications of subcircuits, which correspond with transforms of the subcircuit itself. Using these transforms, the optimum distribution of gain, noise, linearity and power dissipation can be determined. As it turns out, this optimum distribution can even be represented by a simple, analytical expression. This expression predicts that the power dissipation of the DECT front end can be reduced by a factor of 2.7 through an optimum distribution of the specifications. Using these optimum specifications of the subcircuits, the boundaries for further power dissipation reduction can be determined. This is investigated at the system, circuit and technology level. These insights are used in the design of a 2.5GHz wireless local area network, implemented in an optimized technology ("Silicon on Anything"). The power dissipation of the complete receiver is 3.5mW, more than an order of magnitude below other wireless LAN receivers in recent publications. Finally, the combination of this minimum power design method with a platform based development strategy is discussed