Iterative reweighted l1 design of sparse FIR filters

Sparse FIR filters have lower implementation complexity than full filters, while keeping a good performance level. This paper describes a new method for designing 1D and 2D sparse filters in the minimax sense using a mixture of reweighted l1 minimization and greedy iterations. The combination proves to be quite efficient; after the reweighted l1 minimization stage introduces zero coefficients in bulk, a small number of greedy iterations serve to eliminate a few extra coefficients. Experimental results and a comparison with the latest methods show that the proposed method performs very well both in the running speed and in the quality of the solutions obtained

Fir filter design for area efficient implementation /

In this dissertation, a variable precision algorithm based on sensitivity analysis is proposed for reducing the wordlength of the coefficients and/or the number of nonzero bits of the coefficients to reduce the complexity required in the implementation. Further space savings is possible if the proposed algorithm is associated with our optimal structures and derived scaling algorithm. We also propose a structure to synthesize FIR filters using the improved prefilter equalizer structure with arbitrary bandwidth, and our proposed filter structure reduces the area required. Our improved design is targeted at improving the prefilters based on interpolated FIR filter and frequency masking design and aims to provide a sharp transition-band as well as increasing the stopband attenuation. We use an equalizer designed to compensate the prefilter performance. In this dissertation, we propose a systematic procedure for designing FIR filters implementations. Our method yields a good design with low coefficient sensitivity and small order while satisfying design specifications. The resulting hardware implementation is suitable for use in custom hardware such as VLSI and Field Programmable Gate Arrays (FPGAs).FIR filters are preferred for many Digital Signal Processing applications as they have several advantages over IIR filters such as the possibility of exact linear phase, shorter required wordlength and guaranteed stability. However, FIR filter applications impose several challenges on the implementations of the systems, especially in demanding considerably more arithmetic operations and hardware components. This dissertation focuses on the design and implementation of FIR filters in hardware to reduce the space required without loss of performance

Computationally efficient FIR digital filters

Ph.DDOCTOR OF PHILOSOPH

Design of efficient digital interpolation filters for integer upsampling

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaf 44).Digital signal interpolation systems can be implemented in a variety of ways. The most basic interpolation system for integer upsampling cascades an expander unit with an interpolation low-pass filter. More complex implementations can cascade multiple expander and low-pass filter pairs. There is also flexibility in the design of interpolation filters. This thesis explores how digital interpolation systems for integer upsampling can be efficiently implemented. Efficiency is measured in terms of the number of multiplications required for each output sample point. The following factors are studied for their effect on system efficiency: the decomposition of an interpolation system into multiple cascaded stages, the use of recursive and non-recursive interpolation filters, and the use of linear-phase and minimum-phase interpolation filters. In this thesis interpolation systems are designed to test these factors, and their computational costs are calculated. From this data, conclusions are drawn about efficient designs of interpolation systems for integer upsampling.by Daniel B. Turek.M.Eng

Effects of Multirate Systems on the Statistical Properties of Random Signals

In multirate digital signal processing, we often encounter time-varying linear systems such as decimators, interpolators, and modulators. In many applications, these building blocks are interconnected with linear filters to form more complicated systems. It is often necessary to understand the way in which the statistical behavior of a signal changes as it passes through such systems. While some issues in this context have an obvious answer, the analysis becomes more involved with complicated interconnections. For example, consider this question: if we pass a cyclostationary signal with period K through a fractional sampling rate-changing device (implemented with an interpolator, a nonideal low-pass filter and a decimator), what can we say about the statistical properties of the output? How does the behavior change if the filter is replaced by an ideal low-pass filter? In this paper, we answer questions of this nature. As an application, we consider a new adaptive filtering structure, which is well suited for the identification of band-limited channels. This structure exploits the band-limited nature of the channel, and embeds the adaptive filter into a multirate system. The advantages are that the adaptive filter has a smaller length, and the adaptation as well as the filtering are performed at a lower rate. Using the theory developed in this paper, we show that a matrix adaptive filter (dimension determined by the decimator and interpolator) gives better performance in terms of lower error energy at convergence than a traditional adaptive filter. Even though matrix adaptive filters are, in general, computationally more expensive, they offer a performance bound that can be used as a yardstick to judge more practical "scalar multirate adaptation" schemes

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio