A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

High performance CMOS amplifier and phase-locked loop design

Low voltage, high speed and high linearity are three different aspects of the analog circuit performance that designers are trying to achieve. In this dissertation, three design projects targeting these different performance optimizations are introduced.;The first work is a design of a low voltage operational amplifier. In this work, a threshold voltage tuning technique for low voltage CMOS analog circuit design is presented. A 750mV operational amplifier using this technique was designed in a 0.5mum 5V CMOS process with Vtp ≈ -0.9V and Vtn ≈ 0.8V. The active area is 560mum x 760mum. It exhibits a 62dB DC gain and consumes 38muW of power. It works with supply voltages from 0.75V to 1V. Compared to its 5V counterpart consuming the same amount of current, it maintains nearly the same gain bandwidth product of 3.7MHz. This op amp is the FIRST strong inversion op amp that works at a supply voltage below the threshold voltage.;The second is a design of a high speed phase-locked loop for data recovery. A new non-sequential linear phase detector is introduced in this work. Most of the existing phase detectors for data recovery are based on state-machines. The performance of these structures deteriorates rapidly at higher frequencies because of the inadequate settling performance of the flip-flop used to form the state machine. The new phase detector has a speed advantage over the state-machine based designs because it is simple and easy to implement in CMOS technology. Using this phase detector, a PLL was designed in a 0.25mum CMOS process with an active area of 400mum x 290mum. Experimental results show it successfully locks to a 2.1Gbit/s pseudo-random data sequence at 2.3V. It is believed that the architecture is the fastest that has been introduced for data recovery applications.;The third work introduces the design of a highly-linear variable gain amplifier. It achieves high linearity with third harmonic distortion better than -60dB Vopp = 1V at 160MHz in a 0.25mum CMOS process. It has a precise gain step of 6.02dB that is controlled digitally. The linearity performance is achieved with a linearized open loop amplifier configuration. Similar performance could only be achieved using feedback configuration before

Analog CMOS integrated circuit design

Master'sMASTER OF ENGINEERIN

Analysis and design of high-transconductance RF mosfet voltage to-current converters

The research described in this thesis is concerned with analysis and design of "HighTransconductance RF MOSFET Voltage-to-Current (V-I) Converters". Various V-I converter circuits published in the past have been reviewed by the author in order to understand the different techniques employed to improve transconductance (Gt), linear operating range and total harmonic distortion (THO). Throughout this research, the emphasis has been to improve the above mentioned parameters. All the V-I converter circuits reported have been simulated using PSPICE and the results compared with the values obtained by theoretical analysis. Some of the results of this work have been already reported by the author in the technical literature. (See Chapter 9, at the end of this thesis, where reference to two publications by the author is given.) It was essential to obtain accurate CMOS device parameters values, such as Early Voltage, transconductance parameter ratios!! (gm/gds), X (gmbl'gm) and inter-electrode capacitances, to facilitate the design the prQcess. This was achieved using an extensive set of simulations for the transistor operating under different bias conditions. Furthermore, a measurement technique, thought to be novel, for the direct determination of the transconductance ratios!! and X is proposed. In the next part of the work several types of current mirror are compared against the standard current mirrors, using analytical and simulation methods. Furthermore several MOSFET V-I converter designs were critically reviewed to understand the various existing techniques and their limitations. Two novel techniques, Drain-Source Feedback Circuits (DSFCs) and Drain-Gate Feedback Circuits (OGFCs) ere implemented with a new temperature-compensation scheme, designed to operate well in an industrial environment (-40°C - +8S°C). It is found that the best types of V -I converters were the DSFCs which, offer a more accurate value of Gt (3.386mS) and the THO less than -S7dB for a differential input operating range SOOm V at 1 GHz with a 3V total rail voltage. The OGFC circuits were also meet the initial design targets, the value of THO is less then -SOdB, and operating in the Giga hertz frequency range is possible. Preliminary investigation on future work shows promising results

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies