A methodology for hardware-software codesign

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 150-156).Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.by Myron King.Ph.D

A Methodology for Hardware/Software Codesign of Real-Time Systems with SDL/MSC

: The Specification and Description Language (SDL) and Message Sequence Charts (MSC) are playing a major role in the development of complex systems especially in the telecommunication area. SDL and MSC support the description and validation of systems at a higher level of abstraction as conventional languages as C or Pascal. SDL is especially suited for the hierarchical design of parallel and distributed applications. Today the synthesis of software from SDL specifications is already supported by commercial CASE tools as well as many proprietary tools. The high level of abstraction makes SDL a prime candidate as input language for HW/SW codesign. However, SDL is focusing on functional aspects of the system. Thus, there is only very limited support to deal with performance and time aspects. On the other hand, dealing with time and performance is essential with real-time systems and for codesign. In the paper we show how the SDL methodology can be extended to deal with real-time constrai..

A factorization / defactorization methodology based on data flow petri nets for an efficient hardware/software codesign

International audienceFor many years data flow Petri nets have proved their efficiency in modelling parallel processings. Moreover, an automatic method for their design would be greatly useful. The aim of this paper is to present a methodology for hardware / software codesign based on the principle of factorization / defactorization and thus, to obtain an optimized implementation with the best possible compromise between hardware resources amount and latency, while respecting defined constraints. The search of adequate intermediate factorization / defactorization modelling is very important. In fact, an algorithm can be decomposed into a non-parallelizable part and a parallelizable part. On this latest part, a factoriztion may lead to reduce the amount of hardware resources, while a defactorization has influence on latency. The achievement of a unique optimal solution is not insured, but satisfying optimized solutions can be obtained. First results for several factorizations / defactorizations of a Matrix Vector Product Petri Net description are presented and discussed