2,324 research outputs found
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
Depth-Optimized Reversible Circuit Synthesis
In this paper, simultaneous reduction of circuit depth and synthesis cost of
reversible circuits in quantum technologies with limited interaction is
addressed. We developed a cycle-based synthesis algorithm which uses negative
controls and limited distance between gate lines. To improve circuit depth, a
new parallel structure is introduced in which before synthesis a set of
disjoint cycles are extracted from the input specification and distributed into
some subsets. The cycles of each subset are synthesized independently on
different sets of ancillae. Accordingly, each disjoint set can be synthesized
by different synthesis methods. Our analysis shows that the best worst-case
synthesis cost of reversible circuits in the linear nearest neighbor
architecture is improved by the proposed approach. Our experimental results
reveal the effectiveness of the proposed approach to reduce cost and circuit
depth for several benchmarks.Comment: 13 pages, 6 figures, 5 tables; Quantum Information Processing (QINP)
journal, 201
Optimized Surface Code Communication in Superconducting Quantum Computers
Quantum computing (QC) is at the cusp of a revolution. Machines with 100
quantum bits (qubits) are anticipated to be operational by 2020
[googlemachine,gambetta2015building], and several-hundred-qubit machines are
around the corner. Machines of this scale have the capacity to demonstrate
quantum supremacy, the tipping point where QC is faster than the fastest
classical alternative for a particular problem. Because error correction
techniques will be central to QC and will be the most expensive component of
quantum computation, choosing the lowest-overhead error correction scheme is
critical to overall QC success. This paper evaluates two established quantum
error correction codes---planar and double-defect surface codes---using a set
of compilation, scheduling and network simulation tools. In considering
scalable methods for optimizing both codes, we do so in the context of a full
microarchitectural and compiler analysis. Contrary to previous predictions, we
find that the simpler planar codes are sometimes more favorable for
implementation on superconducting quantum computers, especially under
conditions of high communication congestion.Comment: 14 pages, 9 figures, The 50th Annual IEEE/ACM International Symposium
on Microarchitectur
Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers
A massive gap exists between current quantum computing (QC) prototypes, and
the size and scale required for many proposed QC algorithms. Current QC
implementations are prone to noise and variability which affect their
reliability, and yet with less than 80 quantum bits (qubits) total, they are
too resource-constrained to implement error correction. The term Noisy
Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems
of 1000 qubits or less. Given NISQ's severe resource constraints, low
reliability, and high variability in physical characteristics such as coherence
time or error rates, it is of pressing importance to map computations onto them
in ways that use resources efficiently and maximize the likelihood of
successful runs.
This paper proposes and evaluates backend compiler approaches to map and
optimize high-level QC programs to execute with high reliability on NISQ
systems with diverse hardware characteristics. Our techniques all start from an
LLVM intermediate representation of the quantum program (such as would be
generated from high-level QC languages like Scaffold) and generate QC
executables runnable on the IBM Q public QC machine. We then use this framework
to implement and evaluate several optimal and heuristic mapping methods. These
methods vary in how they account for the availability of dynamic machine
calibration data, the relative importance of various noise parameters, the
different possible routing strategies, and the relative importance of
compile-time scalability versus runtime success. Using real-system
measurements, we show that fine grained spatial and temporal variations in
hardware parameters can be exploited to obtain an average x (and up to
x) improvement in program success rate over the industry standard IBM
Qiskit compiler.Comment: To appear in ASPLOS'1
Synthesis of Quantum Logic Circuits
We discuss efficient quantum logic circuits which perform two tasks: (i)
implementing generic quantum computations and (ii) initializing quantum
registers. In contrast to conventional computing, the latter task is nontrivial
because the state-space of an n-qubit register is not finite and contains
exponential superpositions of classical bit strings. Our proposed circuits are
asymptotically optimal for respective tasks and improve published results by at
least a factor of two.
The circuits for generic quantum computation constructed by our algorithms
are the most efficient known today in terms of the number of expensive gates
(quantum controlled-NOTs). They are based on an analogue of the Shannon
decomposition of Boolean functions and a new circuit block, quantum
multiplexor, that generalizes several known constructions. A theoretical lower
bound implies that our circuits cannot be improved by more than a factor of
two. We additionally show how to accommodate the severe architectural
limitation of using only nearest-neighbor gates that is representative of
current implementation technologies. This increases the number of gates by
almost an order of magnitude, but preserves the asymptotic optimality of gate
counts.Comment: 18 pages; v5 fixes minor bugs; v4 is a complete rewrite of v3, with
6x more content, a theory of quantum multiplexors and Quantum Shannon
Decomposition. A key result on generic circuit synthesis has been improved to
~23/48*4^n CNOTs for n qubit
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