Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Digital frequency synthesizer for radar astronomy

The digital frequency synthesizer (DFS) is an integral part of the programmable local oscillator (PLO) which is being developed for the NASA's Deep Space Network (DSN) and radar astronomy. Here, the theory of operation and the design of the DFS are discussed, and the design parameters in application for the Goldstone Solar System Radar (GSSR) are specified. The spectral purity of the DFS is evaluated by analytically evaluating the output spectrum of the DFS. A novel architecture is proposed for the design of the DFS with a frequency resolution of 1/2(exp 48) of the clock frequency (0.35 mu Hz at 100 MHz), a phase resolution of 0.0056 degrees (16 bits), and a frequency spur attenuation of -96 dBc

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Design techniques for low-power wide-band direct digital frequency synthesizers of spread spectrum communication applications

For frequency agile communication systems, fast frequency switching in fine frequency steps with good spectral purity is crucial. Direct Digital Frequency Synthesizer (DDFS) is best suitable for these applications, but is not widely employed in wireless communication systems due to its high power consumption. In general, low power and high integration design are two challenges for mixed signal-circuits and communication systems designers. In this dissertation, new design techniques for DDFS at both architecture and circuit levels are proposed and investigated in order to minimize power consumption and optimize performance. A ROM-less low power wide band DDFS prototype using segmented sine wave Digital-to-Analog Converter (DAC) were designed, fabricated and tested to demonstrate the new design techniques.;First, to further reduce power consumption and save chip area, two new phase interpolation ROM less DDFS architectures are proposed. Segmentation technique is applied to the design of sine wave DAC for DDFS: (1) based upon trigonometric identities, a segmented sine wave DAC with fine nonlinear interpolation DAC\u27s is proposed; (2) based upon first order Taylor series and simple linear interpolation, a segmented sine wave DAC with a fine linear interpolation DAC is proposed. Second, a figure of merit (FM) is defined to find the optimal sine wave DAC segmentations for various resolutions of the segmented sine wave DAC\u27s. The device mismatch effects on the performance of segmented sine wave were also discussed. Third, For DDFS using current-steering segmented sine wave DAC with 12-b phase resolution and 11-b amplitude resolution, a behavioral model in Verilog was used to verify the functionality and validate the architecture. Finally, a DDFS prototype was designed and fabricated in a standard 0.25mum CMOS process. The measured SFDR is better than 50 dB with output frequencies up to 3/8 of the 300 MHz clock frequency. The prototype occupies an active area of 1.4 mm2 and consumes 240 mW for 300 MHz clock frequency. The new techniques reduce the power dissipation and die area substantially when compared to conventional ROM based DDFS designs with on-chip DAC

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Hybrid Synthesizer Based On Phase-Lock Loop (Pll) Driven Direct Digital Synthesizer (Dds)

Throughout the years, the development of a frequency synthesizer has evolved from large and heavy benchtop models to the compact size handheld synthesizer and now in modular form. Due to the fast-growing technology in wireless telecommunication industries and high expenditure or budget allocation to improve the military and defense system, the frequency synthesizer has become one of the highest demand instruments in the market now. The research will focus on conventional Phase-Lock Loop (PLL) and latest technology of Direct Digital Synthesizer (DDS) and combine to become a hybrid PLL driven DDS synthesizer. This research was triggered since there was minimum work that has been covered and undetermined performances for such hybrid design. Furthermore, the problems faced for standalone synthesizers can be overcome through the hybrid system design. Phase noise, switching speed and spectral purity was the performance evaluated for the proposed setup and was compared with a standalone DDS synthesizer. Results shows the FCWS switching speed improved but there was degradation seen on phase noise and spectral purity particularly on the subharmonics and reference spurious. The harmonics and normal mode switching speed shows no difference between both systems. Although there was some performance degradation observed, the proposed setup performances are still under specifications for high performances applications and there are rooms for future improvement to be one of the best synthesizer designs that the market could offer

Exceeding octave tunable Terahertz waves with zepto-second level timing noise

Spectral purity of any millimeter wave (mmW) source is of the utmost interest in low-noise applications. Optical synthesis via photomixing is an attractive source for such mmWs, which usually involves expensive spectrally pure lasers with narrow linewidths approaching monochromaticity due to their inherent fabrication costs or specifications. Here, we report an alternative option for enhancing the spectral purity of inexpensive semiconductor diode lasers via a self-injection locking technique through corresponding Stokes waves from a fiber Brillouin cavity exhibiting greatly improved phase noise levels and large wavelength tunability of ~1.8 nm. We implement a system with two self-injected diode lasers on a common Brillouin cavity aimed at difference frequency generation in the mmW and THz region. We generate tunable sub-mmW (0.3 and 0.5 THz) waves by beating the self-injected two wavelength Stokes light on a uni-travelling carrier photodiode and characterize the noise performance. The sub-mmW features miniscule timing noise levels in the zepto-second (zs.Hz^-0.5) scale outperforming the state of the art dissipative Kerr soliton based micro-resonator setups while offering broader frequency tunability. These results suggest a viable inexpensive alternative for mmW sources aimed at low-noise applications featuring lab-scale footprints and rack-mounted portability while paving the way for chip-scale photonic integration.Comment: 31 page

Method and apparatus for spur-reduced digital sinusoid synthesis

A technique for reducing the spurious signal content in digital sinusoid synthesis is presented. Spur reduction is accomplished through dithering both amplitude and phase values prior to word-length reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output word-length reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M + 1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise power can be made white, making the power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution

LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

Ph.DDOCTOR OF PHILOSOPH

RF hardware design of a stepped frequency continuous wave ground penetrating radar

Bibliography: pages 86-88.Research into stepped frequency continuous wave ground penetrating radar (SFCW GPR) at UCT has been carried out since 1990. A first generation system comprising of Hewlett-Packard test equipment controlled by a PC was assembled. Cavity-backed log spiral antennas were designed and built by the University of Stellenbosch for the specific use of ground penetrating radar. Measurements with the first generation system proved the concept of SFCW GPR and thus a dedicated second generation system was planned. A SFCW GPR system was designed to replace the first generation system. Various designs for transmitter and receiver configurations were investigated and those found most suitable were used for the implementation. The SFCW radar consists of a wideband CW transmitter and a coherent receiver. A 300-1000 MHz transmitter was constructed using varactor-tuned oscillators as frequency sources. A double-sideband, low-IF receiver was constructed for the 300- 1000 MHz signal, to mix it to an IF of 10.7 MHz and I-Q demodulate it. The transmitter was found to operate according to specifications. The receiver was found to operate satisfactorily, but the dynamic range was less than expected. A limiting problem encountered in the first generation GPR was the large direct coupling signal from the transmitter into the receiver. This large signal reduced the effective receiver dynamic range. A method of cancelling this large direct coupling signal was implemented, using a bi-phase modulator to generate the cancelling signal in antiphase to the coupling signal. A 20 dB reduction in coupling was shown. The system was used to measure cable lengths to within the inherent accuracy of the system. A metal plate target was detected by the system feeding two antenna and a concrete floor was detected under 1 m of sand. It was thus shown that the SFCW system could be used as a second generation GPR