Reconfiguration based built-in self-test for analogue front-end circuits

Previous work has shown that it is feasible to implement a fully digital test evaluation function to realise partial self-test on an automatic gain control circuit (AGC). This paper extends the technique to INL, DNL, offset & gain error testing of analogue to digital converters (ADC's). It also shows how the same function can be used to test an AGC / ADC pair. An extension to full self-test is also proposed by the on-chip generation of input stimuli through reconfiguration of existing functions

Analog-to-digital conversion techniques for precision photometry

Three types of analog-to-digital converters are described: parallel, successive-approximation, and integrating. The functioning of comparators and sample-and-hold amplifiers is explained. Differential and integral linearity are defined, and good and bad examples are illustrated. The applicability and relative advantages of the three types of converters for precision astronomical photometric measurements are discussed. For most measurements, integral linearity is more important than differential linearity. Successive-approximation converters should be used with multielement solid state detectors because of their high speed, but dual slope integrating converters may be superior for use with single element solid state detectors where speed of digitization is not a factor. In all cases, the input signal should be tailored so that they occupy the upper part of the converter's dynamic range; this can be achieved by providing adjustable gain, or better by varying the integration time of the observation if possible

Improved test methods for determining lightning-induced voltages in aircraft

A lumped parameter transmission line with a surge impedance matching that of the aircraft and its return lines was evaluated as a replacement for earlier current generators. Various test circuit parameters were evaluated using a 1/10 scale relative geometric model. Induced voltage response was evaluated by taking measurements on the NASA-Dryden Digital Fly by Wire F-8 aircraft. Return conductor arrangements as well as other circuit changes were also evaluated, with all induced voltage measurements being made on the same circuit for comparison purposes. The lumped parameter transmission line generates a concave front current wave with the peak di/dt near the peak of the current wave which is more representative of lightning. However, the induced voltage measurements when scaled by appropriate scale factors (peak current or di/dt) resulting from both techniques yield comparable results

A 14-Bit Pseudo-Differential Current-Source Resistor-String Hybrid Digital-To-Analogue (DAC) Converter With Low Power Consumption

A 14-bit Hybrid DAC circuit is created with the goal of being low power yet maintaining high resolution output and high accuracy. In order to achieve this, binary weighted DAC architecture is used for the 10 LSBs and thermometer coding is used for the 4 MSBs to leverage the advantages of both architectures. Binary Weighted architecture is used due to its simplicity and high linearity but it is too expensive and impractical for higher resolutions. Thermometer coding advantage lie in having very low glitch effect thus improving the monotonicity of the design. Furthermore, this design uses a switchable current source to drive the digital input. The switchable current source is used to manipulate the current gain to ensure a low power design. The design is using predictive technology model (PTM) 45nm 1.1V CMOS technology. It is being simulated using LTSpice software. Simulation Results show a fine resolution step value of 44 μV and a requirement of only 12 μA current supply which results in a very low power consumption of around 23mW. This is superior to all similar works except for binary-weighted current steering DAC which consumes 20mW yet suffers from serious glitch issues

Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

Carbon footprint of 3D-printed bone tissue engineering scaffolds: an life cycle assessment study

The bone tissue engineering scaffolds is one of the methods for repairing bone defects caused by various factors. According to modern tissue engineering technology, three-dimensional (3D) printing technology for bone tissue engineering provides a temporary basis for the creation of biological replacements. Through the generated 3D bone tissue engineering scaffolds from previous studies, the assessment to evaluate the environmental impact has shown less attention in research. Therefore, this paper is aimed to propose the Model of life cycle assessment (LCA) for 3D bone tissue engineering scaffolds of 3D gel-printing technology and presented the analysis technique of LCA from cradle-to-gate for assessing the environmental impacts of carbon footprint. Acrylamide (C3H5NO), citric acid (C6H8O7), N,N-Dimethylaminopropyl acrylamide (C8H16N2O), deionized water (H2O), and 2-Hydroxyethyl acrylate (C5H8O3) was selected as the material resources. Meanwhile, the 3D gel-printing technology was used as the manufacturing processes in the system boundary. The analysis is based on the LCA Model through the application of GaBi software. The environmental impact was assessed in the 3D gel-printing technology and it was obtained that the system shows the environmental impact of global warming potential (GWP). All of the emissions contributed to GWP have been identified such as emissions to air, freshwater, seawater, and industrial soil. The aggregation of GWP result in the stage of manufacturing process for input and output data contributed 47.6% and 32.5% respectively. Hence, the data analysis of the results is expected to use for improving the performance at the material and manufacturing process of the product life cycle

A supercapacitor based enhancement technique for stand-alone surge protection circuits

With the International Technology Roadmap for Semiconductors predicting below-25nm feature-size VLSIs, powered by DC power supplies of less than 1V, protection against transients has become mandatory for modern electronic systems. Surge protection circuits are usually designed using non-linear devices such as metal oxide varistors and semiconductor devices and these devices are rated for short-term energy absorption, based on transient waveforms defined by standards such as IEEE C62.41. Despite their very low voltage DC ratings, supercapacitors are characterized by large time constants and significant continuous energy absorption ratings. This paper presents details of a patent-pending technique where multi-winding magnetic core with a supercapacitor based energy absorber stage can be combined with the commonly used non-linear devices, for enhanced protection. Comparison of the supercapacitor-enhanced circuit together with a commercial surge protection circuit is provided