A High Speed Differential Resistor Ladder

This paper describes the implementation of a novel high-speed differential resistor ladder. In this paper it is shown that the novel ladder yields, theoretically, up to a sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. In order to ease the design process, an accurate analytical model for the ladder INL is also derived in the paper. Simulation results, for a BiCMOS 0.25 μm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design an 8 bit Flash converter. A 65% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8 bit converter