A High-Performance OpenVG Accelerator with Dual-Scanline Filling Rendering

In this paper, we propose a new search algorithm that reduces the memory bandwidth required for finding active edges in OpenVG rendering. It simultaneously prepares an active edge table for each scanline so that one edge may be stored in several active edge tables, which depends on the lifetime of each edge. It also gives us another benefit so that we can implement the multiple scanline filling in parallel for performance improvement. Experimental results show the external memory accesses of the proposed algorithm can be substantially reduced and the performance of the proposed dual-scanline filling rendering architecture can be significantly increased, especially for high-quality images. We implemented an OpenVG accelerator using the dual-scanline filling rendering with one-poly four-metal 0.18- μm CMOS technology, which requires about 350K gates and operates at 100 MHz.This work was supported by System IC2010 project of Korea Ministry of Knowledge Economy and Inter-university Semiconductor Research Center (ISRC), Seoul National University, Seoul. A chip fabrication was supported by Samsung Electronics Ltd. via IDEC