Dynamic Virtual Page-based Flash Translation Layer with Novel Hot Data Identification and Adaptive Parallelism Management

Solid-state disks (SSDs) tend to replace traditional motor-driven hard disks in high-end storage devices in past few decades. However, various inherent features, such as out-of-place update [resorting to garbage collection (GC)] and limited endurance (resorting to wear leveling), need to be reduced to a large extent before that day comes. Both the GC and wear leveling fundamentally depend on hot data identification (HDI). In this paper, we propose a hot data-aware flash translation layer architecture based on a dynamic virtual page (DVPFTL) so as to improve the performance and lifetime of NAND flash devices. First, we develop a generalized dual layer HDI (DL-HDI) framework, which is composed of a cold data pre-classifier and a hot data post-identifier. Those can efficiently follow the frequency and recency of information access. Then, we design an adaptive parallelism manager (APM) to assign the clustered data chunks to distinct resident blocks in the SSD so as to prolong its endurance. Finally, the experimental results from our realized SSD prototype indicate that the DVPFTL scheme has reliably improved the parallelizability and endurance of NAND flash devices with improved GC-costs, compared with related works.Peer reviewe

Toward a Unified Performance and Power Consumption NAND Flash Memory Model of Embedded and Solid State Secondary Storage Systems

This paper presents a set of models dedicated to describe a flash storage subsystem structure, functions, performance and power consumption behaviors. These models cover a large range of today's NAND flash memory applications. They are designed to be implemented in simulation tools allowing to estimate and compare performance and power consumption of I/O requests on flash memory based storage systems. Such tools can also help in designing and validating new flash storage systems and management mechanisms. This work is integrated in a global project aiming to build a framework simulating complex flash storage hierarchies for performance and power consumption analysis. This tool will be highly configurable and modular with various levels of usage complexity according to the required aim: from a software user point of view for simulating storage systems, to a developer point of view for designing, testing and validating new flash storage management systems

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance be- come a serious concern for systems' designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimiza- tion in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reli- ability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full non- volatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system leve

낸드플래시 메모리 셀 간의 문턱전압 변화를 반영한 센싱 시스템 모델링 및 검증 방법

학위논문 (석사) -- 서울대학교 대학원 : 공학전문대학원 응용공학과, 2021. 2. 김재하.The sensing system in NAND flash memories is a complex mixed-signal circuit consisting of a large-scale cell array, wordline decoders, page buffers, analog/digital bit-counters, and digital sequence controllers. This paper proposes a model and simulation framework that can assess the effectiveness of various incremental/adaptive algorithms used by digital controllers for the read, program, and erase operations, while simulating the progression of individual cell threshold voltages (Vth) and modeling the detailed analog characteristics of the page buffers. The proposed model is written entirely in SystemVerilog, and its analog parts are described using the XMODEL primitives, which enable efficient and event-driven simulation of analog circuits. The proposed model can simulate a 40μs-long incremental step pulse programming (ISPP) sequence with the maximum loop iteration count of 4 on a 12K-bit block of single-level cells (SLC) in less than 2 minutes, and can assess the trade-offs between the programming speed and reliability as a function of the pulse step size and the impacts of the page buffers sensing time on the final cell Vth distribution.NAND 플래시 메모리의 센싱 시스템은 대용량의 데이터를 저장할 수 있는 셀 어레이와 이를 구동시키기 위한 워드 라인 디코더, 페이지 버퍼, 아날로그 / 디지털 비트 카운터 및 디지털 시퀀스 컨트롤러로 구성된 복잡한 혼성신호 회로이다. 본 연구에서는 개별 셀의 초기 조건과 특성에 따라 서로 다른 양상을 보이는 문턱 전압 (Vth)의 변화를 반영할 수 있으며, 페이지 버퍼의 특성을 포함한 상세한 아날로그 동작들의 모델링하여 디지털 컨트롤러가 읽기, 프로그램 및 삭제 작업에 사용하는 다양한 알고리즘의 효율성을 평가할 수있는 모델 및 시뮬레이션 프레임 워크를 제안한다. 제안하는 모델은 디지털과 아날로그로 나뉘어진 검증환경이 아닌 하나의 통합된 SystemVerilog기반으로 작성되었으며, 특히 XMODEL 프리미티브를 사용하여 아날로그 회로의 이벤트 기반 시뮬레이션을 통해 효율적인 검증이 가능하게 되었다. 해당 시스템 모델을 기반으로 12K 비트의 단일 레벨 셀 (SLC) 블록에서 최대 루프 반복 횟수가 4 회인 40μs 길이의 ISPP (Incremental Step Pulse Programming) 동작을 2 분 이내에 시뮬레이션 할 수 있었다. 또한, 검증과정을 통해 얻게 되는 개별 셀 Vth 분포 분석을 통해서 프로그래밍 속도와 신뢰성 사이의 관계를 펄스 스텝 크기의 함수로서 표현할 수 있었으며, 페이지 버퍼의 센싱 시간 조절을 통한 최종 셀 Vth 분포의 중심치에 대한 영향에 대해서도 검증가능하다.Chapter 1. Introduction 1 1.1. Study Background 1 1.2. Thesis Organization 3 Chapter 2. Background 4 2.1. NAND Flash Memory Architecture and Its Operations 4 2.2. Previous Works 8 Chapter 3. Proposed SystemVerilog Model of NAND Flash Memory Sensing System 11 3.1. Cell Array Model 12 3.2. Page Buffer Model 15 3.3. Analog Bit-Counter Model 19 3.4. Digital System Model 22 Chapter 4. Experimental Results 23 4.1. SLC Program with Different ISPP Steps 25 4.2. SLC Program with Different Sensing Times 28 Chapter 5. Conclusions 30 Bibliography 31 Appendix 33 Abstract in Korean 40Maste

On the use of NAND flash memory in high-performance relational databases

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 47-49).High-density NAND flash storage has become relatively inexpensive due to the popularity of various consumer electronics. Recently, several manufacturers have released IDE-compatible NAND flash-based drives in sizes up to 64 GB at reasonable (sub-$1000) prices. Because flash is significantly more durable than mechanical hard drives and requires considerably less energy, there is some speculation that large data centers will adopt these devices. As database workloads make up a substantial fraction of the processing done by data centers, it is interesting to ask how switching to flash-based storage will affect the performance of database systems. We evaluate this question using IDE-based flash drives from two major manufacturers. We measure their read and write performance and find that flash has excellent random read performance, acceptable sequential read performance, and quite poor write performance compared to conventional IDE disks. We then consider how standard database algorithms are affected by these performance characteristics and find that the fast random read capability dramatically improves the performance of secondary indexes and index-based join algorithms. We next investigate using logstructured filesystems to mitigate the poor write performance of flash and find an 8.2x improvement in random write performance, but at the cost of a 3.7x decrease in random read performance. Finally, we study techniques for exploiting the inherent parallelism of multiple-chip flash devices, and we find that adaptive coding strategies can yield a 2x performance improvement over static ones. We conclude that in many cases flash disk performance is still worse than on traditional drives and that current flash technology may not yet be mature enough for widespread database adoption if performance is a dominant factor. Finally, we briefly speculate how this landscape may change based on expected performance of next-generation flash memories.by Daniel Myers.S.M

Dependability Assessment of NAND Flash-memory for Mission-critical Applications

It is a matter of fact that NAND flash memory devices are well established in consumer market. However, it is not true that the same architectures adopted in the consumer market are suitable for mission critical applications like space. In fact, USB flash drives, digital cameras, MP3 players are usually adopted to store "less significant" data which are not changing frequently (e.g., MP3s, pictures, etc.). Therefore, in spite of NAND flash's drawbacks, a modest complexity is usually needed in the logic of commercial flash drives. On the other hand, mission critical applications have different reliability requirements from commercial scenarios. Moreover, they are usually playing in a hostile environment (e.g., the space) which contributes to worsen all the issues. We aim at providing practical valuable guidelines, comparisons and tradeoffs among the huge number of dimensions of fault tolerant methodologies for NAND flash applied to critical environments. We hope that such guidelines will be useful for our ongoing research and for all the interested reader

A Flexible BCH decoder for Flash Memory Systems using Cascaded BCH codes

NAND ash memories are widely used in consumer electronics, such as tablets, personal computers, smartphones, and gaming systems. However, unlike other standard storage devices, these ash memories suffer from various random errors. In order to address these reliability issues, various error correction codes (ECC) are employed. Bose-Chaudhuri Hocquenghem (BCH) code is the most common ECC used to address the errors in modern ash memories. Because of the limitation of the realization of the BCH codes for more extensive error correction, the modern ash memory devices use Low-density parity-check (LDPC) codes for error correction scheme. The realization of the LDPC decoders have greater complexity than BCH decoders, so these ECC decoders are implemented within the ash memory device. This thesis analyzes the limitation imposed by the state of the art implementation of BCH decoders and proposes a cascaded BCH code to address these limitations. In order to support a variety of ash memory devices, there are three main challenges to be addressed for BCH decoders. First, the latency of the BCH decoders, in the case of no error scenario, should be less than 100us. Second, there should be flexibility in supporting different ECC block size; more precisely, the solution should be able to support 256, 512, 1024, and 2048 bytes of ECC block. Third, there should be flexibility in supporting different bit errors. A recent development with Graphical Processing Units (GPUs) has attracted many researchers to use GPUs for non-graphical implementation. These GPUs are used in many consumer electronics as part of the system on chip (SOC) configuration. In this thesis we studied the limitation imposed by different implementations (VLSI, GPU, and CPU) of BCH decoders, and we propose a cascaded BCH code implemented using a hybrid approach to overcome the limitations of the BCH codes. By splitting the implementation across VLSI and GPUs, we have shown in this thesis that this method can provide flexibility over the block size and the bit error to be corrected