A high-performance CMOS programmable logic core for system-on-chip applications

Thesis (Ph. D.)--University of Washington, 2005.Integrated circuits (ICs) have experienced an astonishing revolution in the last two decades. As predicted by Moore's law, the integration density doubles approximately every eighteen months. Nowadays hundreds of millions of transistors can be integrated on a chip. To lower the cost, system-on-a-chip (SoC) has emerged as a solution and attracted attention. SoC technology is the packaging of all the necessary functionality, including digital, analog and radio frequency, on a single chip. It has been the hot spot of research for both industry and academic and is becoming the mainstream of IC design.As part of the SoCs, programmable logic cores (PLCs) have become more and more popular for its capability of post-fabrication changes. PLCs provide better flexibility, less cost and shorter time-to-market as well. On the other hand, the post fabrication flexibility sacrifices speed, resulting in a speed gap between fixed logic and programmable logic, and making programmable logic far from mainstream. Typically, a circuit implemented in programmable logic will run about 3 times slower than that implemented in fixed logic [8]. Improving the speed of programmable logic is one of the primary challenges.In this dissertation, a novel high-speed PLC architecture is proposed. By combining a high-performance dynamic logic style (output prediction logic or OPL), a product-term-based structure, mixed logic/routing structures, wired-OR structures and a unidirectional routing flow, this architecture achieves an average speedup of 4.1 times over the Xilinx Virtex-E FPGA [50], a Look-Up-Table (LUT) based architecture using static CMOS. It also can achieve up to a 1 GHz throughput, which is 2.4 times that of the Xilinx CoolRunner-II CPLD [49] and 3.2 times that of the Xilinx Virtex-E FPGA (Speed Grade-7) [50]. Measurement results for a prototype block fabricated in the TSMC 0.18mum/1.8V CMOS process are presented.This thesis work demonstrates that programmable logic can achieve comparable speeds to ASICs with design innovations, and therefore enables the adoption of programmable logic on an SoC